Abstract: The present invention relates to devices for safely locking collapsible furniture in a fixed configuration. In particular, the present invention provides locks for collapsible furniture which are automatically engaged and require multiple affirmative steps to unlock.

Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Abstract: The present invention provides a signal analyzing method for an electronic device having an on-chip network and an off-chip network. Compared with the conventional signal analyzing method for an electronic device having an on-chip network and an off-chip network, the signal analyzing method of the present invention is able to provide a complete electrical connection and accurate electrical characteristics for an electronic device having an on-chip network and an off-chip network.

Abstract: The present invention provides systems and devices for expanding and collapsing a tent, a gazebo, or tent-like structure. In particular, the present invention provides a central support device for supporting a tent, gazebo, or tent-like structure in an expanded configuration and moveably collapsing the tent, gazebo, or tent-like structure into a collapsed configuration.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: The semiconductor structure of the present invention comprises: a P-well, a first N+ diffusion region, a first P+ diffusion region, a second P+ diffusion region, a first N-well, and a second N+ diffusion region. The semiconductor structure of the present invention comprises: a N-well, a first P+ diffusion region, a first N+ diffusion region, a second N+ diffusion region, a first P-well, and a second P+ diffusion region. Compared with the conventional semiconductor structure for realizing an ESD protection circuit, the semiconductor structure of the present invention requires a smaller area by utilizing the parasitic BJT to have the same ESD protection function. Brief summarized, the semiconductor structure disclosed by the present invention can be utilized for realizing an ESD protection circuit in a smaller area to reduce cost.

Abstract: A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.

Abstract: A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.

Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

Abstract: An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.

Abstract: A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.

Abstract: A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.

Abstract: A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.

Abstract: The present invention provides several embodiments with layout patterns for ESD protection. An apparatus with a layout pattern may be configured to protect I/O pads or the power rail. The layout pattern may designed to increase the current paths for ESD stress currents. For example, more rings may be applied. The present invention also provides circuit embodiments for ESD protection. According to one embodiment, an ESD protection circuit comprising four parasitic BJTs may be configured to protect the I/O pads or the power rail. More BJTs or resistors may be used to increase the current paths for ESD stress currents. Several variations and modifications may be made by changing the doping profiles of the doped regions.

Abstract: A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.

Abstract: A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.

Abstract: An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.