Abstract: A dock station and a mini-projector being mutually integrated is provided. The dock station includes a dock station body, a projector interface and a power management unit. The dock station body is employed for connecting at least an electronic apparatus. The projector interface is employed for connecting the mini-projector and the dock station body. The power management unit is disposed in the dock station body. The dock station uses the mini-projector to play AV data in the electronic apparatus.

Abstract: The present invention provides several embodiments with layout patterns for ESD protection. An apparatus with a layout pattern may be configured to protect I/O pads or the power rail. The layout pattern may designed to increase the current paths for ESD stress currents. For example, more rings may be applied. The present invention also provides circuit embodiments for ESD protection. According to one embodiment, an ESD protection circuit comprising four parasitic BJTs may be configured to protect the I/O pads or the power rail. More BJTs or resistors may be used to increase the current paths for ESD stress currents. Several variations and modifications may be made by changing the doping profiles of the doped regions.

Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped region and a second conductive type third doped region. The first well region is located within the substrate and the second well region is located within the first well region. The first doped region is located within the first well region and detached from the second well region but adjacent to the surface of the substrate. The second doped region and the third doped region are located within the second well region and adjacent to the surface of the substrate. The second doped region is located between the first doped region and the third doped region but detached from both the first doped region and the third doped region.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract: A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped region and a second conductive type third doped region. The first well region is located within the substrate and the second well region is located within the first well region. The first doped region is located within the first well region and detached from the second well region but adjacent to the surface of the substrate. The second doped region and the third doped region are located within the second well region and adjacent to the surface of the substrate. The second doped region is located between the first doped region and the third doped region but detached from both the first doped region and the third doped region.

Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. All collectors of the parasitic bipolar transistors are connected to an anode terminal. The guard ring, the first/second longitudinal doped regions and all emitters of the parasitic bipolar transistors are connected to a cathode terminal.

Abstract: High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, high doping concentration ions implanted into active D/S regions formed a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. In an original drain JBV of an MOS this ESDI method is unchanged, i.e.

Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. All collectors of the parasitic bipolar transistors are connected to an anode terminal. The guard ring, the first/second longitudinal doped regions and all emitters of the parasitic bipolar transistors are connected to a cathode terminal.

Abstract: An electrostatic discharge (ESD) protection device. The ESD protection device includes a first parasitic bipolar transistor, a second parasitic bipolar transistor, a third parasitic bipolar transistor and a fourth parasitic bipolar transistor formed over a substrate. A first longitudinal doped region is formed between the first parasitic bipolar transistor and the second parasitic bipolar transistor. Similarly, a second longitudinal doped region is formed between the third parasitic bipolar transistor and the fourth parasitic bipolar transistor. A guard ring circumscribes the substrate. An isolation region is formed inside the guard ring. The guard ring and the first/second longitudinal doped region are all connected to a ground terminal.

Abstract: In this invention, a novel substrate-triggered technique is proposed to effectively improve the electrostatic discharge (ESD) robustness of integrated circuit (IC) products. The ESD protection circuit derived from the substrate-triggered technique is comprised of a metal-oxide-semiconductor (MOS) transistor and an ESD detection circuit. The MOS transistor is composed of a bulk region, a gate, a source region coupled to a power rail, and a drain region couple to a pad. The source region, the bulk region and the drain region further construct a parasitic bipolar junction transistor (BJT) The ESD detection circuit is located between, and connected to, the power rail and the pad. During normal operation, the ESD detection circuit maintains the coupling of the bulk region to the first power rail. During an ESD event, the ESD detection circuit biases the bulk region to trigger the BJT thereby releasing ESD stress.

Abstract: An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, implant high doping concentration ions into active D/S regions forming a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. The original drain JBV of an MOS with this ESDI method is unchanged, i.e.

Abstract: An ESD (electrostatic discharge) protection circuit is electrically connected to an I/O buffering pad, an internal circuit (IC), a VSS power terminal and a VDD power terminal. The ESD protection circuit comprises a first ESD-detection circuit electrically connected between the I/O pad and the VSS power terminal, a second ESD-detection circuit electrically connected between the I/O pad and the VDD power terminal, a P-STSCR comprising a first lateral SCR and a P trigger node, and an N-STSCR comprising a second lateral SCR and an N trigger node. When a positive-to-VSS ESD event occurs on the I/O buffering pad, the first ESD-detection circuit generates a first trigger current to the P-trigger node of the P-STSCR to trigger the first lateral SCR. The P-STSCR is thus quickly turned on, and current incurred from the positive voltage pulse is discharged to the VSS power terminal.

Abstract: A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.

Abstract: A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.