Abstract: An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, implant high doping concentration ions into active D/S regions forming a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. The original drain JBV of an MOS with this ESDI method is unchanged, i.e.

Abstract: An ESD protection device is formed on a P-type well, and has at least one NMOS, at least one first P+ diffusion region for electrically connecting to a P-well biasing circuit, at least one dummy gate between the NMOS and the first P+ diffusion region, at least one second P+ diffusion region for electrically connecting to a VSS power terminal, and at least one shallow trench isolation (STI) structure for isolating the NMOS and the second P+ diffusion region. A drain of the NMOS, the P-type well, and a source of the NMOS form a parasitic lateral n-p-n bipolar junction transistor (BJT), and the drain and the source of the NMOS are electrically connected to an I/O buffering pad and a VSS power terminal respectively. When an ESD voltage pulse zaps the I/O buffering pad, the P-well biasing circuit induces a substrate trigger current (Itrig), causing the parasitic lateral n-p-n BJT to trigger on and quickly discharge a current incurred from the ESD voltage pulse.

Abstract: A process for forming an implanted ESD region, and for forming metal silicide blocking regions, using the same photolithographic mask for definition of these regions, has been developed. The process features the formation of an implanted ESD region, defined by a photoresist shape which in turn had been formed via exposure of a negative photoresist layer, using a specific photolithographic mask. Metal silicide regions are subsequently formed on regions of a semiconductor substrate, exposed in openings in an insulator layer, with the openings in the insulator layer defined via a photoresist shape, which in turn had been formed via exposure of a positive photoresist layer, using the same photolithographic mask previously used for definition of the implanted ESD region. In this invention we use only one photolithographic mask in the CMOS process to fabricate an ESD device having ESD implanted and metal silicide blocking regions, which can sustain higher ESD stress.

Abstract: A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.