Patents by Inventor Tung Yang

Tung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9508086
    Abstract: Methods and apparatus to monitor, verify, and rate the performance of airings of commercials are disclosed. An example method includes analyzing received advertisement detection information associated with the advertisement, the advertisement detection information detected from a presentation of the advertisement; identifying a buy order corresponding to the presentation of the advertisement based on the advertisement detection information; determining a purchased ratings value from the buy order; comparing the purchased ratings value of the buy order to received ratings information corresponding to the presentation of the advertisement to determine whether the advertisement was presented as indicated in the buy order; and generating a performance monitoring report using the buy order and the advertisement detection information to indicate whether the ratings information is less than the purchased ratings value.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 29, 2016
    Assignee: THE NIELSEN COMPANY (US), LLC
    Inventors: James Milton Rathburn, Laurence Blair Miller, Thomas J. Whymark, Huaiyeu Huey Yu, Hui-Tung Yang, Stephen Shindle, Jonathan Chazen, Joseph Kaminski
  • Publication number: 20160320908
    Abstract: A touch input device includes a planar location sensing board, a depth sensing layer, a first interpretation unit, a second interpretation unit, and a processing unit. The planar location sensing board senses a first electrical variation of different locations in the directions parallel to the planar location sensing board due to an object approaching or touching the planar location sensing board. The depth sensing layer is disposed below the planar location sensing board and separated by a distance from the planar location sensing board. The depth sensing layer senses a second electrical variation corresponding to a degree in which the object presses the planar location sensing board. The first interpretation unit is electrically connected to the planar location sensing board. The second interpretation unit is electrically connected to the depth sensing layer. The processing unit determines a three-dimensional touch location of the object. A touch sensing method is also provided.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Sweehan J.H. Yang, Tung-Yang Tang, Wen-Hua Chang, Yong-Yu Chen
  • Patent number: 9481020
    Abstract: Bending members having slanted faces to engage folded edge portions of a housing panel, wherein the relative sliding movement between the folded edge portions and the bending members cause bending of each of the folded edge portions to an inwardly slanted angle.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 1, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhi-Jie Wang, Ming-Jen Yu, Tung-Yang Hu, Kevin L. Massaro, Chun-Pu Chen, Dimitre D. Mehandjiysky
  • Publication number: 20160313067
    Abstract: A heat dissipating device includes a heat dissipating fin and a heat pipe. The heat dissipating fin includes a fin body, a through hole, a first arc-shaped portion and a second arc-shaped portion. The through hole is formed on the fin body and has a central line. The first arc-shaped portion extends from the through hole in a first direction and the second arc-shaped portion extends from the through hole in a second direction, wherein the first direction is opposite to the second direction. The first arc-shaped portion and the second arc-shaped portion are located at opposite sides of the central line. The heat pipe is disposed in the through hole.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Inventors: Tung-Yang Shieh, Shih-Yi Chang
  • Publication number: 20160284687
    Abstract: A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A second semiconductor region is in the first semiconductor region. A third semiconductor region is in the first semiconductor region. A fourth semiconductor region is outside the first semiconductor region. A fifth semiconductor region is outside the first semiconductor region to a fifth depth, the fifth semiconductor region being adjacent the fourth semiconductor region. A sixth semiconductor region is below the fifth semiconductor region and to a sixth depth. The sixth depth is equal to the first depth. A first electrode is connected to the third semiconductor region. A second electrode is connected to the fourth and fifth semiconductor regions. The fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation between the first and second electrodes.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: Hsin-Chih CHIANG, Tung-Yang LIN, Ruey-Hsin LIU, Ming-Ta LEI
  • Patent number: 9431531
    Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Yang Lin, Hsin-Chih Chiang, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20160247914
    Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu
  • Patent number: 9417744
    Abstract: A touch input device including a carrying board, a plurality of first electrode pads, and a plurality of conductive lines is provided. The carrying board includes a plurality of cantilever portions and a plurality of connecting portions. The connecting portions are respectively connected to the cantilever portions. The first electrode pads are respectively disposed on the cantilever portions and configured to sense capacitance variation due to an object approaching or touching the carrying board. The conductive lines extend on the connecting portions and are respectively connected to the first electrode pads. A manufacturing method of a touch input device and a touch sensing method are also provided.
    Type: Grant
    Filed: April 6, 2014
    Date of Patent: August 16, 2016
    Assignee: Wistron Corporation
    Inventors: Sweehan J. H. Yang, Tung-Yang Tang, Wen-Hua Chang, Yong-Yu Chen
  • Patent number: 9412863
    Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 9379179
    Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: June 28, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20160181422
    Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20160173052
    Abstract: A power EMI suppression filter is connected to a power feeding line of a main functional IC and other loads. The main functional IC driven by a power source supplied by the power feeding line generates an output voltage and current which are individually involved with an output voltage interference and output current interference, and a phase difference exits there-in-between. A reference providing circuit generates a first reference signal according to the output voltage interference and/or the output current interference. A primary filtering circuit calculates eigenvalues of the output voltage interference and/or the output current interference according to the first reference signal to generate a second reference signal. A secondary filtering circuit calculates eigenvalues again based on the second signal so the phase difference and amplitudes of the interferences are zero. Thus, an output voltage and current signal the load receives are DC signal without interferences.
    Type: Application
    Filed: March 9, 2015
    Publication date: June 16, 2016
    Inventor: TUNG-YANG CHEN
  • Publication number: 20160173053
    Abstract: A power shunt EMI filter is electrically connected to a power feeding line of a main functional IC and other loads. The main functional IC driven by a power source supplied by the power feeding line generates an output voltage and an output current which are individually involved with an output voltage interference and an output current interference, and a phase difference exits there-in-between. A reference providing circuit generates a reference signal according to the output voltage interference and/or the output current interference. At least one adjust filtering circuit calculates eigenvalues of the output voltage interference and/or the output current interference according to the reference signal, such that the phase difference and amplitudes of the interferences are zero. Thus, an output voltage signal and current signal the load receives are DC signal without interferences.
    Type: Application
    Filed: March 9, 2015
    Publication date: June 16, 2016
    Inventor: TUNG-YANG CHEN
  • Patent number: 9356139
    Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu
  • Patent number: 9300853
    Abstract: Disclosed is a network camera data management system for managing camera data of a network camera, including: a data importing device, a splitting and storing device, and a data retrieving device. A management method utilized by the network camera data management system includes the steps of: splitting the imported camera data into a camera audio data and a camera video data based on the respective data formats; storing the camera audio data and the camera video data respectively in different servers and/or in different server storage areas that have non-sequential storage addresses with each other in one server; and retrieving, according to a retrieval condition, a fragment of the camera audio data and/or a fragment of the camera video data from the camera audio data and/or the camera video data stored.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 29, 2016
    Assignee: AMARYLLO INTERNATIONAL INC.
    Inventors: Chao-Tung Yang, Kuang-Jui Cheng, Wen-Kuang Lin
  • Publication number: 20150379125
    Abstract: Disclosed is a network camera data management system for managing camera data of a network camera, including: a data importing device, a segmenting and storing device, and a data capture device. A management method utilized by the network camera data management system includes the steps of: segmenting the imported camera data into a plurality of time segmented data items based on time intervals; storing the plurality of time segmented data items respectively in a plurality of servers and/or in a plurality of server storage areas having non-sequential storage addresses with each other; and capturing, according to a search condition, a corresponding time segmented data item and/or a fragment of the corresponding time segmented data item of the from the plurality of time segmented data items stored.
    Type: Application
    Filed: October 24, 2014
    Publication date: December 31, 2015
    Inventors: CHAO-TUNG YANG, KUANG-JUI CHENG, WEN-KUANG LIN
  • Publication number: 20150381875
    Abstract: Disclosed is a network camera data management system for managing camera data of a network camera, including: a data importing device, a splitting and storing device, and a data retrieving device. A management method utilized by the network camera data management system includes the steps of: splitting the imported camera data into a camera audio data and a camera video data based on the respective data formats; storing the camera audio data and the camera video data respectively in different servers and/or in different server storage areas that have non-sequential storage addresses with each other in one server; and retrieving, according to a retrieval condition, a fragment of the camera audio data and/or a fragment of the camera video data from the camera audio data and/or the camera video data stored.
    Type: Application
    Filed: October 28, 2014
    Publication date: December 31, 2015
    Inventors: CHAO-TUNG YANG, KUANG-JUI CHENG, WEN-KUANG LIN
  • Publication number: 20150343510
    Abstract: Bending members having slanted faces to engage folded edge portions of a housing panel, wherein the relative sliding movement between the folded edge portions and the bending members cause bending of each of the folded edge portions to an inwardly slanted angle.
    Type: Application
    Filed: January 29, 2013
    Publication date: December 3, 2015
    Inventors: Zhijie Wang, Ming-Jen Yu, Tung-Yang Hu, Kevin L. Massaro, Chun-Pu Chen, Dimitre D. Mehandjiysky
  • Patent number: D749445
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 16, 2016
    Assignee: AMARYLLO INTERNATIONAL B.V.
    Inventor: Chao-Tung Yang
  • Patent number: D749661
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Amaryllo International B.V.
    Inventors: Chao-Tung Yang, Shu-Hua Liu, Cheng-Po Chen