Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path.

Abstract: Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command.

Abstract: A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold.

Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

Abstract: A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.