Patents by Inventor Tza-Jing Gung
Tza-Jing Gung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948846Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.Type: GrantFiled: April 4, 2023Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Patent number: 11915918Abstract: A physical vapor deposition processing chamber is described. The processing chamber includes a target backing plate in a top portion of the processing chamber, a substrate support in a bottom portion of the processing chamber, a deposition ring positioned at an outer periphery of the substrate support and a shield. The substrate support has a support surface spaced a distance from the target backing plate to form a process cavity. The shield forms an outer bound of the process cavity. In-chamber cleaning methods are also described. In an embodiment, the method includes closing a bottom gas flow path of a processing chamber to a process cavity, flowing an inert gas from the bottom gas flow path, flowing a reactant into the process cavity through an opening in the shield, and evacuating the reaction gas from the process cavity.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Jothilingam Ramalingam, Yong Cao, Ilya Lavitsky, Keith A. Miller, Tza-Jing Gung, Xianmin Tang, Shane Lavan, Randy D. Schmieding, John C. Forster, Kirankumar Neelasandra Savandaiah
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Patent number: 11898236Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.Type: GrantFiled: October 20, 2021Date of Patent: February 13, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Zhiyong Wang, Halbert Chong, John C. Forster, Irena H. Wysok, Tiefeng Shi, Gang Fu, Renu Whig, Keith A Miller, Sundarapandian Ramalinga Vijayalakshmi Reddy, Jianxin Lei, Rongjun Wang, Tza-Jing Gung, Kirankumar Neelasandra Savandaiah, Avinash Nayak, Lei Zhou
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Publication number: 20230238289Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.Type: ApplicationFiled: April 4, 2023Publication date: July 27, 2023Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Publication number: 20230154726Abstract: Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film. In one embodiment, a plurality of retaining brackets is disposed in a rotational magnetic housing of the magnetic housing systems. Each retaining bracket of the plurality of retaining brackets is disposed in the rotational magnetic housing with a distance d between each retaining bracket. The plurality of retaining brackets has a plurality of magnets removably disposed therein. The plurality of magnets is configured to travel in a circular path when the rotational magnetic housing is rotated around the round central opening.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Inventors: Srinivas GANDIKOTA, Tza-Jing GUNG, Samuel E. GOTTHEIM, Timothy Joseph FRANKLIN, Pramit MANNA, Eswaranand VENKATASUBRAMANIAN, Edward HAYWOOD, Stephen C. GARNER, Adam FISCHBACH
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Patent number: 11637043Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.Type: GrantFiled: November 3, 2020Date of Patent: April 25, 2023Assignee: Applied Materials, Inc.Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Patent number: 11637107Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: GrantFiled: June 17, 2021Date of Patent: April 25, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Publication number: 20230122956Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Inventors: Zhiyong WANG, Halbert CHONG, John C. FORSTER, Irena H. WYSOK, Tiefeng SHI, Gang FU, Renu WHIG, Keith A. MILLER, Sundarapandian Ramalinga Vijayalakshmi REDDY, Jianxin LEI, Rongjun WANG, Tza-Jing GUNG, Kirankumar Neelasandra SAVANDAIAH, Avinash NAYAK, Lei ZHOU
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Publication number: 20230113514Abstract: Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.Type: ApplicationFiled: December 3, 2021Publication date: April 13, 2023Applicant: Applied Materials, Inc.Inventors: Shih Chung Chen, Yongjing Lin, Chi-Chou Lin, Zhiyong Wang, Chih-Hsun Hsu, Mandyam Sriram, Tza-Jing Gung
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Patent number: 11626410Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: GrantFiled: July 11, 2022Date of Patent: April 11, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Patent number: 11587764Abstract: Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film. In one embodiment, a plurality of retaining brackets is disposed in a rotational magnetic housing of the magnetic housing systems. Each retaining bracket of the plurality of retaining brackets is disposed in the rotational magnetic housing with a distance d between each retaining bracket. The plurality of retaining brackets has a plurality of magnets removably disposed therein. The plurality of magnets is configured to travel in a circular path when the rotational magnetic housing is rotated around the round central opening.Type: GrantFiled: November 1, 2019Date of Patent: February 21, 2023Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Tza-Jing Gung, Samuel E. Gottheim, Timothy Joseph Franklin, Pramit Manna, Eswaranand Venkatasubramanian, Edward Haywood, Stephen C. Garner, Adam Fischbach
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Patent number: 11562909Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.Type: GrantFiled: May 22, 2020Date of Patent: January 24, 2023Assignee: Applied Materials, Inc.Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
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Publication number: 20220415636Abstract: A physical vapor deposition processing chamber is described. The processing chamber includes a target backing plate in a top portion of the processing chamber, a substrate support in a bottom portion of the processing chamber, a deposition ring positioned at an outer periphery of the substrate support and a shield. The substrate support has a support surface spaced a distance from the target backing plate to form a process cavity. The shield forms an outer bound of the process cavity. In-chamber cleaning methods are also described. In an embodiment, the method includes closing a bottom gas flow path of a processing chamber to a process cavity, flowing an inert gas from the bottom gas flow path, flowing a reactant into the process cavity through an opening in the shield, and evacuating the reaction gas from the process cavity.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Jothilingam Ramalingam, Yong Cao, Ilya Lavitsky, Keith A. Miller, Tza-Jing Gung, Xianmin Tang, Shane Lavan, Randy D. Schmieding, John C. Forster, Kirankumar Neelasandra Savandaiah
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Publication number: 20220415637Abstract: A physical vapor deposition processing chamber is described. The processing chamber includes a target backing plate in a top portion of the processing chamber, a substrate support in a bottom portion of the processing chamber, a deposition ring positioned at an outer periphery of the substrate support and a shield. The substrate support has a support surface spaced a distance from the target backing plate to form a process cavity. The shield forms an outer bound of the process cavity. In-chamber cleaning methods are also described. In an embodiment, the method includes closing a bottom gas flow path of a processing chamber to a process cavity, flowing an inert gas from the bottom gas flow path, flowing a reactant into the process cavity through an opening in the shield, and evacuating the reaction gas from the process cavity.Type: ApplicationFiled: July 11, 2022Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Jothilingam Ramalingam, Yong Cao, Ilya Lavitsky, Keith A. Miller, Tza-Jing Gung, Xianmin Tang, Shane Lavan, Randy D. Schmieding, John C. Forster, Kirankumar Neelasandra Savandaiah
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Publication number: 20220406790Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: ApplicationFiled: July 11, 2022Publication date: December 22, 2022Applicant: Applied Materials, Inc.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Publication number: 20220406788Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: Applied Materials, Inc.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Publication number: 20220336223Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.Type: ApplicationFiled: June 22, 2022Publication date: October 20, 2022Applicant: Applied Materials, Inc.Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
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Publication number: 20220310364Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Publication number: 20220310363Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Patent number: 11339475Abstract: An apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes are provided. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.Type: GrantFiled: November 8, 2019Date of Patent: May 24, 2022Assignee: Applied Materials, Inc.Inventors: Xinhai Han, Deenesh Padhi, Daemian Raj Benjamin Raj, Kristopher Enslow, Wenjiao Wang, Masaki Ogata, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Gregory Eugene Chichkanoff, Shailendra Srivastava, Jonghoon Baek, Zakaria Ibrahimi, Juan Carlos Rocha-Alvarez, Tza-Jing Gung