Patents by Inventor Tze-Chiang Chen

Tze-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solar cell made using a barrier layer between P-type and intrinsic layers
    Patent number: 9537038
    Abstract: A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 3, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTD
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Jeehwan Kim, Devendra K. Sadana, Chih-Fu Tseng
  • Ambipolar synaptic devices
    Patent number: 9472641
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: April 11, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • SEMICONDUCTOR DEVICE WITH PROGRAMMABLE RESPONSE
    Publication number: 20160197294
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Application
    Filed: February 16, 2016
    Publication date: July 7, 2016
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • SEMI-CONDUCTOR DEVICE WITH PROGRAMMABLE RESPONSE
    Publication number: 20160197296
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Application
    Filed: February 15, 2016
    Publication date: July 7, 2016
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Semi-conductor device with programmable response
    Patent number: 9379342
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Semiconductor device with programmable response
    Patent number: 9379340
    Abstract: An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • Heterojunction light emitting diode
    Patent number: 9343616
    Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • COST-EFFICIENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS
    Publication number: 20160111576
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: TZE-CHIANG CHEN, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Ambipolar synaptic devices
    Patent number: 9318572
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Semi-conductor device with programmable response
    Patent number: 9318717
    Abstract: An apparatus with a programmable response includes a semi-conductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semi-conductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: April 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark
  • INTERDIGITATED BACK CONTACT HETEROJUNCTION PHOTOVOLTAIC DEVICE
    Publication number: 20160079463
    Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 17, 2016
    Inventors: TZE-CHIANG CHEN, BAHMAN HEKMATSHOARTABARI, DEVENDRA K. SADANA, DAVOOD SHAHRJERDI
  • SOLAR CELL MADE USING A BARRIER LAYER BETWEEN P-TYPE AND INTRINSIC LAYERS
    Publication number: 20160071995
    Abstract: A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.
    Type: Application
    Filed: November 13, 2015
    Publication date: March 10, 2016
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Jeehwan Kim, Devendra K. Sadana, Chih-Fu Tseng
  • HYBRID JUNCTION FIELD-EFFECT TRANSISTOR AND ACTIVE MATRIX STRUCTURE
    Publication number: 20160035989
    Abstract: Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Heterojunction light emitting diode
    Patent number: 9252324
    Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Junction field-effect floating gate quantum dot memory switch
    Patent number: 9245896
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Junction field-effect quantum dot memory switch
    Patent number: 9246113
    Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES
    Publication number: 20160020344
    Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: TZE-CHIANG CHEN, BAHMAN HEKMATSHOARTABARI, DEVENDRA K. SADANA, DAVOOD SHAHRJERDI
  • AMBIPOLAR SYNAPTIC DEVICES
    Publication number: 20150380517
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Application
    Filed: September 5, 2015
    Publication date: December 31, 2015
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Embedded junction in hetero-structured back-surface field for photovoltaic devices
    Patent number: 9202959
    Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: December 1, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Solar cell made using a barrier layer between p-type and intrinsic layers
    Patent number: 9190549
    Abstract: A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 17, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTD
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Jeehwan Kim, Devendra K. Sadana, Chih-Fu Tseng