Patents by Inventor Tze-Chiang Chen
Tze-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7498235Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: GrantFiled: October 25, 2007Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 7435652Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.Type: GrantFiled: March 30, 2007Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
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Publication number: 20080241369Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks.Type: ApplicationFiled: May 2, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Stuart S.P. Parkin
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Publication number: 20080242070Abstract: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang
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Patent number: 7416905Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks.Type: GrantFiled: October 17, 2005Date of Patent: August 26, 2008Assignee: International Busniess Machines CorporationInventors: Tze-chiang Chen, Stuart S. P. Parkin
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Publication number: 20080050887Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: ApplicationFiled: October 25, 2007Publication date: February 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Guy Cohen, Alexander Reznicek, Devendra Sadana, Ghavam Shahidi
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Patent number: 7315065Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: GrantFiled: July 6, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
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Publication number: 20070278586Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
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Publication number: 20070152276Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Arnold, Glenn Biery, Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Michael Gribelyuk, Young-Hee Kim, Barry Linder, Vijay Narayanan, Joseph Newbury, Vamsi Paruchuri, Michelle Steen
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Publication number: 20070152273Abstract: A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUNISESS MACHINES CORPORATIONInventors: Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Young-Hee Kim, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen, Ying Zhang
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Publication number: 20070087454Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/ or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks.Type: ApplicationFiled: October 17, 2005Publication date: April 19, 2007Inventors: Tze-chiang Chen, Stuart Parkin
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Publication number: 20060289948Abstract: The present invention provides a metal stack (or gate stack) structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a gate conductor and a dielectric material having a dielectric constant of greater than about 4.0, especially a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing an alkaline earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a high k dielectric, preferably a hafnium-based dielectric; an alkaline earth metal-containing layer located atop of, or within, said high k dielectric; an electrically conductive capping layer located above said high k dielectric; and a gate conductor.Type: ApplicationFiled: June 22, 2005Publication date: December 28, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Brown, Tze-Chiang Chen, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7138319Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.Type: GrantFiled: January 10, 2005Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Kiang-Kai Han
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Publication number: 20060249790Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: ApplicationFiled: July 6, 2006Publication date: November 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Guy Cohen, Alexander Reznicek, Devendra Sadana, Ghavam Shahidi
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Patent number: 7108797Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.Type: GrantFiled: February 25, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Stuart S. P. Parkin
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Patent number: 7084460Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: GrantFiled: November 3, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Guy M. Cohen, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
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Publication number: 20060105559Abstract: A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from about 100 angstroms to about 1 micron and annealing the substrate at a temperature from 1200° C. to 1400°0 C. in an oxygen containing atmosphere. The invention over comes the problem of the buried oxide breaking up into oxide islands during the anneal.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Applicant: International Business Machines CorporationInventors: Tze-Chiang Chen, Bernard Meyerson, Devendra Sadana
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Patent number: 6955926Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.Type: GrantFiled: February 25, 2004Date of Patent: October 18, 2005Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Stuart S. P. Parkin
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Publication number: 20050186686Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.Type: ApplicationFiled: February 25, 2004Publication date: August 25, 2005Applicant: International Business Machines CorporationInventors: Tze-chiang Chen, Stuart Parkin
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Patent number: 6914320Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.Type: GrantFiled: March 23, 2004Date of Patent: July 5, 2005Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu