Patents by Inventor Tzu-Ching Tsai
Tzu-Ching Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527493Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer.Type: GrantFiled: November 30, 2021Date of Patent: December 13, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tzu-Ching Tsai
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Publication number: 20220148963Abstract: A method for forming an integrated circuit device includes providing a first substrate having a first conductive portion, providing a second substrate having a second conductive portion, performing a first chemical reaction to form a first expanding pad on the first conductive portion to provide a first expanded contact area, performing a second chemical reaction to form a second expanding pad on the second conductive portion to provide a second expanded contact area, and bonding the first substrate to the second substrate with a bonding structure.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Inventor: TZU-CHING TSAI
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Patent number: 11315871Abstract: An integrated circuit device includes a first substrate, a second substrate, a first expanding pad, a second expanding pad and a bonding structure. The first substrate is provided with a first conductive portion, the second substrate is provided with a second conductive portion, the first expanding pad is formed on the first conductive portion to provide a first expanded contact area, the second expanding pad is formed on the second conductive portion to provide a second expanded contact area, and the bonding structure is formed between the first substrate and the second substrate, wherein the first expanding pad is bonded to the second expanding pad.Type: GrantFiled: June 13, 2019Date of Patent: April 26, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tzu-Ching Tsai
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Patent number: 11309263Abstract: The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features.Type: GrantFiled: May 11, 2020Date of Patent: April 19, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tzu-Ching Tsai
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Publication number: 20220093533Abstract: The present disclosure provides a method for preparing a semiconductor device structure.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Inventor: TZU-CHING TSAI
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Patent number: 11264474Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a pad oxide layer positioned on the substrate, a hard mask layer positioned on the pad oxide layer, an isolation layer positioned along the hard mask layer and the pad oxide layer and extending to the substrate, a first dielectric layer positioned between the substrate and the isolation layer, and a liner layer positioned on a top surface of the hard mask layer and positioned between the first dielectric layer and the isolation layer, between the pad oxide layer and the isolation layer, and between the hard mask layer and the isolation layer. The hard mask layer and the liner layer include boron nitride.Type: GrantFiled: August 18, 2020Date of Patent: March 1, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tzu-Ching Tsai
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Publication number: 20220059666Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a pad oxide layer positioned on the substrate, a hard mask layer positioned on the pad oxide layer, an isolation layer positioned along the hard mask layer and the pad oxide layer and extending to the substrate, a first dielectric layer positioned between the substrate and the isolation layer, and a liner layer positioned on a top surface of the hard mask layer and positioned between the first dielectric layer and the isolation layer, between the pad oxide layer and the isolation layer, and between the hard mask layer and the isolation layer. The hard mask layer and the liner layer include boron nitride.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Inventor: TZU-CHING TSAI
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Publication number: 20210351140Abstract: The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Inventor: Tzu-Ching TSAI
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Patent number: 11057708Abstract: A diaphragm for a micro loudspeaker includes an outer casing that is provided with a through-hole, a membrane that is disposed in the through-hole, and a suspension that connects the membrane and the outer casing. The outer casing is provided with an inner wall that wraps into the through-hole. The suspension includes an effective operation zone that is extended from the inner wall into the through-hole, and a fixed area that is extended from the inner wall to outside the through-hole. The fixed area of the suspension is provided with a cut-off area, which keeps the effective operation zone at a good intactness, and enables the membrane to vibrate up and down more uniformly, thereby improving the sound quality of micro loudspeaker.Type: GrantFiled: December 31, 2019Date of Patent: July 6, 2021Assignee: CONCRAFT HOLDING CO., LTD.Inventors: Lei Cheng, Yankui Zhuang, Tzu-Ching Tsai
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Patent number: 11011522Abstract: The present application discloses a semiconductor device with nanowire plugs and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of capacitor contacts positioned over the second regions, at least one of the capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the first regions and a plurality of bit lines positioned over the bit line contacts; a plurality of capacitor plugs disposed over the capacitor contacts, wherein at least one of the plurality of capacitor plugs includes a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and a plurality of capacitor structures disposed respectively over the capacitor plugs.Type: GrantFiled: September 25, 2019Date of Patent: May 18, 2021Assignee: Nanya Technologies CorporationInventor: Tzu-Ching Tsai
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Publication number: 20210136497Abstract: A diaphragm for a micro loudspeaker includes an outer casing that is provided with a through-hole, a membrane that is disposed in the through-hole, and a suspension that connects the membrane and the outer casing. The outer casing is provided with an inner wall that wraps into the through-hole. The suspension includes an effective operation zone that is extended from the inner wall into the through-hole, and a fixed area that is extended from the inner wall to outside the through-hole. The fixed area of the suspension is provided with a cut-off area, which keeps the effective operation zone at a good intactness, and enables the membrane to vibrate up and down more uniformly, thereby improving the sound quality of micro loudspeaker.Type: ApplicationFiled: December 31, 2019Publication date: May 6, 2021Inventors: Lei CHENG, Yankui ZHUANG, Tzu-Ching TSAI
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Publication number: 20210091088Abstract: The present application discloses a semiconductor device with nanowire plugs and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of capacitor contacts positioned over the second regions, at least one of the capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the first regions and a plurality of bit lines positioned over the bit line contacts; a plurality of capacitor plugs disposed over the capacitor contacts, wherein at least one of the plurality of capacitor plugs includes a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and a plurality of capacitor structures disposed respectively over the capacitor plugs.Type: ApplicationFiled: September 25, 2019Publication date: March 25, 2021Inventor: Tzu-Ching TSAI
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Publication number: 20200395295Abstract: An integrated circuit device includes a first substrate, a second substrate, a first expanding pad, a second expanding pad and a bonding structure. The first substrate is provided with a first conductive portion, the second substrate is provided with a second conductive portion, the first expanding pad is formed on the first conductive portion to provide a first expanded contact area, the second expanding pad is formed on the second conductive portion to provide a second expanded contact area, and the bonding structure is formed between the first substrate and the second substrate, wherein the first expanding pad is bonded to the second expanding pad.Type: ApplicationFiled: June 13, 2019Publication date: December 17, 2020Inventor: TZU-CHING TSAI
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Patent number: 10788607Abstract: The present invention discloses a Fresnel lens with a light receiving effect, including a converging surface and an incidence surface opposite to the converging surface. The incidence surface is provided with an optically effective refractive region and an optically reflective region annularly surrounding the optically effective refractive region. The optically reflective region is provided at least with a prism annularly disposed outside the optically effective refractive region. The prism is provided with a refraction surface which is in adjacent to the optically effective refractive region and a reflection surface which is disposed at a first angle relative to the refraction surface. In addition, a tail end of the prism is an inverted hook part. Therefore, the effective working area of the refraction surface and the reflection surface can be increased, thereby improving the light receiving effect of the Fresnel lens.Type: GrantFiled: August 2, 2018Date of Patent: September 29, 2020Assignee: CONCRAFT HOLDING CO., LTD.Inventors: Tzu-Ching Tsai, Jie-Ru Chen
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Publication number: 20200281773Abstract: An earplug, which is inserted and worn inside a person's ear canal, consists of a main guide body provided with a compression portion, a supporting stem provided with an air passage and used to support the main guide body, and a filler material provided with plasticity that fills the compression portion. A filling cavity is provided inside the compression portion that interconnects with the air passage and enables filling with the filler material, and causes an air chamber that connects to the air passage to form inside the compression portion, enabling the compression portion to form an original state. The compression portion is in a compressed state when pressed and constricted, and air circulating in the air passage is used to cause changes in the compression portion between its original state and compressed state, which enables enhancing comfortability when wearing the earplug.Type: ApplicationFiled: June 3, 2019Publication date: September 10, 2020Inventors: Jie-Ru CHEN, Tzu-Ching TSAI
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Patent number: 10705264Abstract: A varifocal lens module, consisting of a casing provided with a holding chamber, an opening end, an interconnecting hole, a soft lens disposed on the casing to seal the holding chamber, and a medium control device connects to the interconnecting hole. The soft lens is provided with a first curved surface having a first curvature exposed external of the casing and a second curved surface having a second curvature positioned interior of the holding chamber corresponding to the first curved surface. The medium control device is connected to the interconnecting hole for controlling the volume of the medium inside the holding chamber, whereby the change in volume of the medium changes the compression on the second curved surface, thereby modifying the second curvature of the second curved surface, producing a variation in the spacing between the second curved surface and the first curved surface to achieve a varifocal effect.Type: GrantFiled: August 2, 2018Date of Patent: July 7, 2020Assignee: CONCRAFT HOLDING CO., LTD.Inventors: Tzu-Ching Tsai, Jie-Ru Chen
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Publication number: 20190302324Abstract: A varifocal lens module, consisting of a casing provided with a holding chamber, an opening end, an interconnecting hole, a soft lens disposed on the casing to seal the holding chamber, and a medium control device connects to the interconnecting hole. The soft lens is provided with a first curved surface having a first curvature exposed external of the casing and a second curved surface having a second curvature positioned interior of the holding chamber corresponding to the first curved surface. The medium control device is connected to the interconnecting hole for controlling the volume of the medium inside the holding chamber, whereby the change in volume of the medium changes the compression on the second curved surface, thereby modifying the second curvature of the second curved surface, producing a variation in the spacing between the second curved surface and the first curved surface to achieve a varifocal effect.Type: ApplicationFiled: August 2, 2018Publication date: October 3, 2019Inventors: Tzu-Ching TSAI, Jie-Ru CHEN
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Publication number: 20190302323Abstract: The present invention discloses a Fresnel lens with a light receiving effect, including a converging surface and an incidence surface opposite to the converging surface. The incidence surface is provided with an optically effective refractive region and an optically reflective region annularly surrounding the optically effective refractive region. The optically reflective region is provided at least with a prism annularly disposed outside the optically effective refractive region. The prism is provided with a refraction surface which is in adjacent to the optically effective refractive region and a reflection surface which is disposed at a first angle relative to the refraction surface. In addition, a tail end of the prism is an inverted hook part. Therefore, the effective working area of the refraction surface and the reflection surface can be increased, thereby improving the light receiving effect of the Fresnel lens.Type: ApplicationFiled: August 2, 2018Publication date: October 3, 2019Inventors: Tzu-Ching TSAI, Jie-Ru CHEN
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Publication number: 20130102123Abstract: A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.Type: ApplicationFiled: October 19, 2011Publication date: April 25, 2013Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Tzu-Ching Tsai, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8335119Abstract: A method of inspecting a memory cell is provided, including: providing a semiconductor substrate with a capacitor formed therein and a transistor formed thereon, wherein the transistor is electrically connected to the capacitor; inspecting a size of a top surface of the capacitor and a pitch between the capacitor and the transistor electrically connected thereto by an optical measuring system, thereby obtaining a first measurement data and a second measurement data; and comparing the first and second measurement data with designed specifications of the capacitor and transistor, thereby determining functionality of the memory cell comprising the capacitor and the transistor.Type: GrantFiled: October 19, 2011Date of Patent: December 18, 2012Assignee: Nanya Technology CorporationInventors: Tzu-Ching Tsai, Yi-Nan Chen, Hsien-Wen Liu