Abstract: A process for integrating an alignment mark and a trench device. A substrate having first and second trenches is provided. The second trench is used as the alignment mark having a width larger than the first trench. The trench device is formed in each of the low portion of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. A second conductive layer is formed overlying the substrate and fills in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. The second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by the etch back process.

Abstract: A process for integration of a trench for capacitors and removal of black silicon. A semiconductor substrate is etched to form a capacitor trench having a predetermined depth, and black silicon spikes are generated on the semiconductor substrate at the edge region. A thermal oxide film is grown conformally on the capacitor trench. A sacrificial layer is then formed on the semiconductor substrate at the memory cell region, wherein the sacrificial layer is filled into the capacitor trench. The black silicon spikes are removed while the sacrificial layer is used as the shield. The sacrificial layer is partially removed to expose the thermal oxide film. The exposed thermal oxide film is then removed. Finally, the residual sacrificial structure is removed.

Abstract: A process for filling a polysilicon seam. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.

Abstract: Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

Abstract: A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

Abstract: Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

Abstract: A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.

Abstract: A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.

Abstract: A method for forming a bottle-shaped trench. A semiconductor substrate having a pad stack layer thereon and a trench in a predetermined position is provided. A first dielectric layer is then formed on the lower sidewalls of the trench. Next, a second dielectric layer is formed to cover the upper sidewalls of the trench and the pad stack layer. Then, a protection layer is formed on the sidewalls portions of the second dielectric layer. The first dielectric layer is then removed to expose the lower portion of trench. Wet stripping is then carried out to increase the radius of the lower portion of the trench thereby forming a bottle-shaped trench.

Abstract: A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.

Abstract: A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

Abstract: A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The aspect ratio of the opening is 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

Abstract: A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.

Abstract: A process for integration of a trench for capacitors and removal of black silicon. A semiconductor substrate is etched to form a capacitor trench having a predetermined depth, and black silicon spikes are generated on the semiconductor substrate at the edge region. A thermal oxide film is grown conformally on the capacitor trench. A sacrificial layer is then formed on the semiconductor substrate at the memory cell region, wherein the sacrificial layer is filled into the capacitor trench. The black silicon spikes are removed while the sacrificial layer is used as the shield. The sacrificial layer is partially removed to expose the thermal oxide film. The exposed thermal oxide film is then removed. Finally, the residual sacrificial structure is removed.

Abstract: A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.

Abstract: A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.

Abstract: A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.

Abstract: A method for removing black silicon in semiconductor fabrication is disclosed. First, a trench is formed in a semiconductor substrate having a pad dielectric layer and a hard mask layer. Then, the hard mask layer is removed. A photoresist layer covers the trench and only black silicon created at the edge of the semiconductor substrate during formation of the trench is left uncovered. Finally, the black silicon is removed.