Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930202
    Abstract: A display apparatus includes a driving substrate and a plurality of micro light-emitting devices (LEDs). The driving substrate has a plurality of pixel regions. The plurality micro LEDs are disposed in in each of the pixel regions and electrically connected to the driving substrate. Orthogonal projection areas of the micro LEDs in each of the pixel regions on the driving substrate are equal. At least two micro LEDs in each of the pixel regions have different effective light-emitting areas.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 23, 2021
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Tzu-Yang Lin, Mi-Hung Lai, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Ying-Tsang Liu
  • Patent number: 10923527
    Abstract: A micro LED display panel includes a display area, a plurality of micro light-emitting elements and a plurality of micro control elements. The plurality of micro light-emitting elements is disposed in the display area and include a plurality of first color micro LEDs and a plurality of second color micro LEDs. A light wavelength of each of the first color micro LEDs is different from a light wavelength of each of the second color micro LEDs. The plurality of micro control elements is disposed in the display area, and include a plurality of first color micro circuit-chips and a plurality of second color micro circuit-chips. The plurality of first color micro circuit-chips control the plurality of first color micro LEDs, and the plurality of second color micro circuit-chips control the plurality of second color micro LEDs.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 16, 2021
    Assignee: PixeLED Display CO., LTD.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20210035930
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an antenna device and semiconductor package. The antenna device includes a conductive pattern layer including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate. The antenna device also includes a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The semiconductor package includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer. The semiconductor package also includes a first semiconductor die electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first semiconductor die.
    Type: Application
    Filed: June 24, 2020
    Publication date: February 4, 2021
    Inventors: Yen-Yao CHI, Nai-Wei LIU, Tzu-Hung LIN
  • Patent number: 10903198
    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 26, 2021
    Assignee: MEDIATEK INC
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin
  • Publication number: 20210005614
    Abstract: Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Chang-Hung Lin, Feng-Jung Chang, Tzu-Ming Ou Yang
  • Publication number: 20210005554
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Publication number: 20200409254
    Abstract: The present disclosure provides an apparatus for mounting a pellicle to a photomask, including a presser, a pellicle stage facing the presser, and a flexible material layer between the presser and the pellicle stage, wherein the flexible material layer includes a compartment filled with gas.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: TZU HAN LIU, CHIH-WEI WEN, CHUNG-HUNG LIN
  • Patent number: 10879306
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 29, 2020
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chih-Ling Wu, Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Yu-Yun Lo, Yi-Min Su, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200388736
    Abstract: A method for fabricating a micro light-emitting diode display is provided. The method includes disposing a plurality of micro light-emitting diodes on a carrier; transferring the micro light-emitting diodes from the carrier to a display substrate and disposing the micro light-emitting diodes in a plurality of pixels of the display substrate; subjecting the micro light-emitting diodes to a pre-bonding process to electrically connect the micro light-emitting diodes to the display substrate; subjecting the micro light-emitting diodes pre-bonded to the display substrate to a first detection process, thereby identifying whether a faulty micro light-emitting diode is present or not; and, subjecting the micro light-emitting diodes to the main bonding process after the first detection process.
    Type: Application
    Filed: December 26, 2019
    Publication date: December 10, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yi-Ching CHEN, Pei-Hsin CHEN, Yi-Chun SHIH, Tzu-Yang LIN, Yu-Hung LAI
  • Publication number: 20200381325
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20200379323
    Abstract: A lens includes a casing, a first lens group, a second lens group and a heat dissipating member. The first lens group is disposed in the casing and close to a first side of the casing. The second lens group is disposed in the casing and close to a second side of the casing, wherein the first side is opposite to the second side. The heat dissipating member is disposed at the second side of the casing and contacts the casing.
    Type: Application
    Filed: April 26, 2020
    Publication date: December 3, 2020
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu, Sheng-Wen Hu, Hsin-Jung Yeh, Chih-Chieh Tsung
  • Publication number: 20200365526
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Publication number: 20200357956
    Abstract: A semiconductor light-emitting device includes a substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate, wherein the first semiconductor layer includes a first exposed portion and a second portion; a plurality of first trenches formed on the substrate and including a surface composed by the first exposed portion; a second trench formed on the substrate and including a surface composed by the second exposed portion at a periphery region of the semiconductor light-emitting device, wherein each of the plurality of first trenches is branched from the second trench; and a patterned metal layer formed on the second semiconductor layer and including a first metal region and a second metal region, and portions of the second metal region are formed in the plurality of first trenches and the second trench to electrically connect to the first exposed portion and the second exposed portion.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
  • Patent number: 10833220
    Abstract: A method for manufacturing a micro light emitting diode device is provided. A connection layer and epitaxial structures are formed on a substrate. A first pad is formed on each of the epitaxial structures. A first adhesive layer is formed on the connection layer, and the first adhesive layer encapsulates the epitaxial structures and the first pads. A first substrate is connected to the first adhesive layer. The substrate is removed, and a second substrate is connected to the connection layer through a second adhesive layer. The first substrate and the first adhesive layer are removed. The connection layer located between any two adjacent epitaxial structures are partially removed to form a plurality of connection portions. Each of the connection portions is connected to the corresponding epitaxial structure, and a side edge of each of the connection portions protrudes from a side wall surface of the corresponding epitaxial structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 10, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200350466
    Abstract: A micro light emitting diode chip having a plurality of light-emitting regions, including a semiconductor epitaxial structure, a first electrode and a plurality of second electrodes disposed at interval is provided. The semiconductor epitaxial structure includes a first-type doped semiconductor layer, a plurality of second-type doped semiconductor layers and a plurality of light-emitting layers disposed at interval. The light-emitting layers are located between the first-type doped semiconductor layer and the second-type doped semiconductor layer. The light-emitting layers are located in the light-emitting regions respectively and electrically contact to the first-type doped semiconductor layer. The first electrode is electrically connected and contacts to the first-type doped semiconductor layers. The second electrodes are electrically connected to the second-type doped semiconductor layers. Furthermore, a display panel is also provided.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Applicant: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Yu-Yun Lo, Tzu-Yang Lin
  • Publication number: 20200350113
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Feng-Lung CHIEN, Tsang-Feng WU, Yuan HAN, Tzu-Chieh KAO, Chien-Hung LIN, Kuang-Lun LEE, Hsiang-Hui HSU, Shu-Yi TSUI, Kuo-Jui LEE, Kun-Ying LEE, Mao-Chun CHEN, Tai-Hsien YU, Wei-Yu CHEN, Yi-Ju LI, Kuei-Yuan CHANG, Wei-Chun LI, Ni-Ni LAI, Sheng-Hao LUO, Heng-Sheng PENG, Yueh-Hui KUAN, Hsiu-Chen LIN, Yan-Bing ZHOU, Chris T. Burket
  • Publication number: 20200310243
    Abstract: The present disclosure provides a photomask, including a front side having a patterned layer, a back side opposite to the front side, a sidewall connecting the front side and the back side, a reflective layer between the front side and the back side, and a polymer layer on the backside of the photomask.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Inventors: TZU HAN LIU, CHIH-WEI WEN, CHUNG-HUNG LIN
  • Publication number: 20200312663
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 1, 2020
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yi-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20200312732
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Inventors: Yen-Yao CHI, Nai-Wei LIU, Ta-Jen YU, Tzu-Hung LIN, Wen-Sung HSU, Shih-Chin LIN
  • Publication number: 20200303352
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang