Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385463
    Abstract: An optical engine module including a display panel, a transflective layer, a polarizing reflective layer, a first bifocal lens, a first and second electrically controlled half waveplate is provided. The transflective layer is disposed between the display panel and the polarizing reflective layer. The polarizing reflective layer is configured to allow the light beam having a first polarization state to pass through, and reflect the light beam having a second polarization state. The first and second electrically controlled half waveplate are disposed between the transflective layer and the polarizing reflective layer. The first bifocal lens disposed between the first and second electrically controlled half waveplate has a first focal length for the light beam with the first polarization state, and has a second focal length for the light beam with the second polarization state.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 21, 2024
    Applicant: Coretronic Corporation
    Inventors: Tzu-Hung Lin, Chung-Yang Fang, Wen-Chun Wang, Ching-Chuan Wei, Bo-Han Cheng, Wei-Ting Wu
  • Patent number: 12142598
    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: November 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20240274518
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first substrate having a first wiring structure; and a second substrate having a second wiring structure, wherein the first substrate and the second substrate are arranged side-by-side, and the first substrate and the second substrate are surrounded and separated by a molding material. The semiconductor package structure also includes a redistribution layer disposed over the first substrate and the second substrate, wherein the redistribution layer is electrically coupled to the first wiring structure and the second wiring structure; and a frame surrounding the first substrate and the second substrate.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Inventors: Tzu-Hung LIN, Yuan-Chin LIU
  • Patent number: 12002742
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: June 4, 2024
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Yuan-Chin Liu
  • Publication number: 20240153887
    Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 11948895
    Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: April 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
  • Patent number: 11942439
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yung-Chang Lien
  • Publication number: 20240036429
    Abstract: An electrically controlled optical screen including a switchable scattering element and an electrically controlled decorating module is provided. The switchable scattering element is disposed on a side of the electrically controlled decorating module and is configured to switch between a scattering state and a transparent state. The electrically controlled decorating module includes a first polarizer, a first quarter-wave plate, a cholesteric liquid crystal layer, an electrically controlled wave plate, a second quarter-wave plate and a second polarizer, which are sequentially stacked. The electrically controlled wave plate has a liquid crystal layer. The second polarizer is disposed between the switchable scattering element and the second quarter-wave plate.
    Type: Application
    Filed: June 25, 2023
    Publication date: February 1, 2024
    Applicant: Coretronic Corporation
    Inventors: Ping-Yen Chen, Wen-Chun Wang, Chung-Yang Fang, Jing-Yu Wu, Ching-Chuan Wei, Wei-Ting Wu, Tzu-Hung Lin
  • Patent number: 11862578
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: January 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Patent number: 11854784
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: December 26, 2023
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 11824020
    Abstract: An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: November 21, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Tzu-Hung Lin
  • Patent number: 11791266
    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: October 17, 2023
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11742564
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11728292
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 15, 2023
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang, Che-Ya Chou
  • Patent number: 11688655
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: June 27, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20230197684
    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 22, 2023
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
  • Publication number: 20230187377
    Abstract: A semiconductor package includes a base film, a semiconductor die on the base film, metal studs on the semiconductor die, shielding pillars on the base film and around the semiconductor die, a first molding compound encapsulating the semiconductor die, the metal studs, and the shielding pillars, a first re-distribution structure on the first molding compound, a second molding compound on the first re-distribution structure, through-mold-vias in the second molding compound, and a second re-distribution structure on the second molding compound and electrically connected to the through-mold-vias. The second re-distribution structure comprises an antenna.
    Type: Application
    Filed: November 16, 2022
    Publication date: June 15, 2023
    Applicant: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chih-Ming Hung, Shih-Chia Chiu
  • Patent number: 11652273
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: May 16, 2023
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Yeh-Chun Kao, Shih-Huang Yeh, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11646295
    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: May 9, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20230073399
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 9, 2023
    Applicant: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin