Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941260
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: April 10, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Chi-Chin Lien, Nai-Wei Liu, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 9899261
    Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Publication number: 20170373038
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 28, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Publication number: 20170338175
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Application
    Filed: April 7, 2017
    Publication date: November 23, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Publication number: 20170316218
    Abstract: The present invention provides a method of preventing pry for random access memory. A functional interface is designed between a computer program and a random access memory. When the computer program wants to store an original data into the random access memory, an encryption procedure is processed on the original data first, and then stoic into the random access memory for being an encrypted data. When the computer program ants to fetch related data float the random access memory, the functional interface is used to fetch the encrypted data for decryption, so that the original data is obtained for calculation.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Publication number: 20170316663
    Abstract: The present invention provides a monitor for dynamic displaying. K cameras are connected with the monitor in order to display images recorded by the k cameras on a screen of the monitor. An “abnormality detection algorithm” is used for detecting abnormalities of the images recorded by the k cameras. Those images having abnormalities are displayed continuously on the screen, other images having no abnormality are not displayed, so that a security service personnel can watch those images having abnormalities on the screen to enable appropriate action quickly.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Patent number: 9786560
    Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Patent number: 9786632
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Publication number: 20170287877
    Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Patent number: 9781171
    Abstract: The present invention provides a registration method for managing NAT shutdown. In Internet communication field, a user must perform registrations intermittently to a server through NAT, and increase the time interval of registration step by step. But NAT itself will shutdown if no packet is passed through for a long period. The registration method of the present invention is to adjust the time interval of registration step by step so that the time interval of registration is slightly less than the shutdown time of NAT, and then fix the time interval of registration to assure that all of the Invite packet can pass through without blocking up by the shutdown of NAT.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 3, 2017
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Shaw Hwa Hwang, Cheng Yu Yeh, Kuan Lin Chen, Yao Hsing Chung, Chi Jung Huang, Li Te Shen, Shun Chieh Chang, Bing Chih Yao, Chao Ping Chu, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Publication number: 20170278832
    Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO
  • Publication number: 20170250165
    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 31, 2017
    Inventors: Ming-Tzong YANG, Wei-Che HUANG, Tzu-Hung LIN
  • Publication number: 20170243826
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 24, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Nai-Wei LIU, Wei-Che HUANG
  • Publication number: 20170243814
    Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventors: Jia-Wei Fang, Tzu-Hung Lin
  • Publication number: 20170228399
    Abstract: The present invention provides a method of searching for multimedia image. When a camera and a microphone are used for recording an image file, a software of speech recognition is used for converting the speech recorded by the microphone into a text file, and then the image file and the text file are combined to form a folder for storing into a data base. If a user wants to search for a certain image file, the data base is entered to search all folders, and a key word is used for searching the related text files so that the related image files are very easy to find.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Patent number: 9711488
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 9704836
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20170186676
    Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Wen-Sung HSU, Tzu-Hung LIN, Ta-Jen YU
  • Publication number: 20170179055
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Tzu-Hung LIN, Cheng-Chou HUNG
  • Patent number: 9679842
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 13, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin