Patents by Inventor Tzu-Hung Lin
Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150145127Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Wen-Sung HSU, Tzu-Hung LIN, Ta-Jen YU
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Patent number: 9042376Abstract: In SIP network environment, a general NAT traversal method will become invalid when an NAT with ICMP (Internet Control Message Protocol) is met. The present invention provides four sessions for SIP, i.e. Login Session, Port Prediction Session, Synchronization Session and Media Session, and the SIP network environment includes a first Internet telephone, a second Internet telephone, a first symmetric NAT, a second symmetric NAT and an SIP proxy server. The first symmetric NAT and the second symmetric NAT are ICMP-sensitive. In the Synchronization Session, the first Internet telephone and the second Internet telephone are designed to transmit packets synchronously to avoid port locking.Type: GrantFiled: February 27, 2013Date of Patent: May 26, 2015Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventors: Shaw Hwa Hwang, Bing Chih Yao, Chao Ping Chu, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
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Patent number: 9040359Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.Type: GrantFiled: September 10, 2014Date of Patent: May 26, 2015Assignee: MEDIATEK INC.Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
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Publication number: 20150115406Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.Type: ApplicationFiled: May 21, 2014Publication date: April 30, 2015Applicant: MediaTek Inc.Inventors: Tzu-Hung LIN, Cheng-Chou HUNG
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Publication number: 20150091158Abstract: A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die to the second die such that the first die and the second die are electrically connected; and at least one bonding wire, for electrically connecting the first die to the conductive units or the substrate.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Applicant: MEDIATEK INC.Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
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Patent number: 8987897Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.Type: GrantFiled: May 17, 2011Date of Patent: March 24, 2015Assignee: Mediatek Inc.Inventors: Kuei-Ti Chan, Tzu-Hung Lin, Ching-Liou Huang
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Patent number: 8957518Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.Type: GrantFiled: September 14, 2012Date of Patent: February 17, 2015Assignee: Mediatek Inc.Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
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Publication number: 20150035131Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes a substrate. A chip is disposed on the substrate. A stiffener is disposed on the substrate. The thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: Media Tek Singapore Pte. Ltd.Inventors: Uming KO, Tzu-Hung LIN, Tai-Yu CHEN
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Publication number: 20140377913Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: Thomas Matthew GREGORICH, Andrew C. CHANG, Tzu-Hung LIN
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Patent number: 8859340Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.Type: GrantFiled: January 14, 2014Date of Patent: October 14, 2014Assignee: MediaTek Inc.Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
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Publication number: 20140286331Abstract: In SIP network environment, a general traversal method for a port restricted NAT will become invalid when other users break in. The present invention provides four sessions for SIP, i.e. Login Session, Port Prediction Session, Multi-Traversal Session and Media Session, and the SIP network environment includes a first Internet telephone, a second Internet telephone, a symmetric NAT, a port-restricted NAT and an SIP proxy server. In the Multi-Traversal Session, the second Internet telephone sends a plurality of identical speech packets to consecutive ports of the symmetric NAT through a fixed port of the port-restricted NAT so as to achieve the NAT traversal.Type: ApplicationFiled: April 2, 2013Publication date: September 25, 2014Applicant: National Taipei University of TechnologyInventors: Shaw Hwa Hwang, Cheng Yu Yeh, Kuan Lin Chen, Yao Hsing Chung, Chi Jung Huang, Li Te Shen, Shun Chieh Chang, Bing Chih Yao, Chao Ping Chu, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
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Publication number: 20140241339Abstract: In SIP network environment, a general NAT traversal method will become invalid when an NAT with ICMP (Internet Control Message Protocol) is met. The present invention provides four sessions for SIP, i.e. Login Session, Port Prediction Session, Synchronization Session and Media Session, and the SIP network environment includes a first Internet telephone, a second Internet telephone, a first symmetric NAT, a second symmetric NAT and an SIP proxy server. The first symmetric NAT and the second symmetric NAT are ICMP-sensitive. In the Synchronization Session, the first Internet telephone and the second Internet telephone are designed to transmit packets synchronously to avoid port locking.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventors: Shaw Hwa Hwang, Bing Chih Yao, Chao Ping Chu, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
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Publication number: 20140191396Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: MEDIA TEK INC.Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG
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Publication number: 20140151867Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: MediaTek Inc.Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG
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Publication number: 20140127865Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: MediaTek Inc.Inventors: Thomas Matthew GREGORICH, Andrew C. CHANG, Tzu-Hung LIN
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Publication number: 20140091481Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Applicant: MediaTek Inc.Inventors: Tzu-Hung LIN, Ching-Liou HUANG, Thomas Matthew GREGORICH
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Publication number: 20140035095Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.Type: ApplicationFiled: December 20, 2012Publication date: February 6, 2014Applicant: Media Tek Inc.Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG
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Patent number: 8633588Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.Type: GrantFiled: December 21, 2011Date of Patent: January 21, 2014Assignee: Mediatek Inc.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Publication number: 20130286910Abstract: The present invention provides a power saving system for smart mobile communication device in Internet communication. The power saving system comprises two smart mobile communication devices with Internet connection capability, an Internet, a server, a gateway and a mobile communication network. The two smart mobile communication devices cut off the Internet connection usually. When a smart mobile communication device performs a call through the Internet to the other smart mobile communication device, the server, the gateway and the mobile communication network are used to inform the other smart mobile communication device for Internet connection. After both sides stop the Internet communication, the two smart mobile communication devices cut off the Internet connection.Type: ApplicationFiled: October 12, 2012Publication date: October 31, 2013Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventors: Shaw Hwa Hwang, Ning Yun Ku, Chao Ping Chu, Tzu Hung Lin, Bing Chih Yao
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Publication number: 20130256878Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.Type: ApplicationFiled: March 15, 2013Publication date: October 3, 2013Applicant: MEDIATEK INC.Inventors: Wen-Sung HSU, Tzu-Hung LIN, Ta-Jen YU