Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20170278832
    Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO
  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20170250165
    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 31, 2017
    Inventors: Ming-Tzong YANG, Wei-Che HUANG, Tzu-Hung LIN
  • FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170243826
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 24, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Nai-Wei LIU, Wei-Che HUANG
  • SEMICONDUCTOR PACKAGE
    Publication number: 20170243814
    Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventors: Jia-Wei Fang, Tzu-Hung Lin
  • METHOD OF SEARCHING FOR MULTIMEDIA IMAGE
    Publication number: 20170228399
    Abstract: The present invention provides a method of searching for multimedia image. When a camera and a microphone are used for recording an image file, a software of speech recognition is used for converting the speech recorded by the microphone into a text file, and then the image file and the text file are combined to form a folder for storing into a data base. If a user wants to search for a certain image file, the data base is entered to search all folders, and a key word is used for searching the related text files so that the related image files are very easy to find.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Semiconductor package assembly
    Patent number: 9711488
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Semiconductor package assembly
    Patent number: 9704836
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • SEMICONDUCTOR PACKAGE
    Publication number: 20170186676
    Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Wen-Sung HSU, Tzu-Hung LIN, Ta-Jen YU
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20170179055
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Tzu-Hung LIN, Cheng-Chou HUNG
  • Semiconductor package assembly
    Patent number: 9679842
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 13, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
  • Semiconductor package
    Patent number: 9679830
    Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: June 13, 2017
    Assignee: MEDIATEK INC.
    Inventors: Jia-Wei Fang, Tzu-Hung Lin
  • Semiconductor package
    Patent number: 9659893
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 23, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
  • Microelectronic package with surface mounted passive element
    Patent number: 9660017
    Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 23, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chao-Yang Yeh, Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang
  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20170141041
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 18, 2017
    Inventors: Tzu-Hung LIN, Nai-Wei LIU, I-Hsuan PENG, Wei-Che HUANG
  • Semiconductor package with trace covered by solder resist
    Patent number: 9640505
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 2, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
  • Semiconductor package
    Patent number: 9633936
    Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 25, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Tzu-Hung Lin, Ta-Jen Yu
  • SEMICONDUCTOR PACKAGE ASSEMBLY WITH THROUGH SILICON VIA INTERCONNECT
    Publication number: 20170110406
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN, Kuei-Ti CHAN, Ruey-Beei WU, Kai-Bin WU
  • Semiconductor structure
    Patent number: 9620580
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Cheng-Chou Hung
  • STACKED FAN-OUT PACKAGE STRUCTURE
    Publication number: 20170098629
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: July 25, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • FAN-OUT WAFER LEVEL PACKAGE STRUCTURE
    Publication number: 20170098589
    Abstract: A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG