Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.

Abstract: A hand tool structure has two plier bodies pivoted by a pivot member, and a knob mechanism for controlling opening and closing of the two plier bodies. Opposing sides of the two plier bodies each include a V-shaped groove to form a square clamping hole when the two plier bodies are closed; a row of teeth; a first cutting portion for cutting an electric wire or cable; a second cutting portion for cutting a metal wire; a wavy peeling portion having curved sections, wherein when the two plier bodies are closed, the curved sections form receiving holes with different diameters. The two plier bodies have first and second cutting holes for cutting screws. The first cutting hole includes a large diameter section and a small diameter section. The second cutting hole is greater than the large diameter section, and its extending direction is inclined relative to the first cutting hole.

Abstract: A tracking device including an image sensor, a light source and a processor is provided. The image sensor senses reflected light or scattered light formed by the light source illuminating a work surface. The processor calculates a trace of the tracking device according to one of the reflected light and the scattered light that generates more apparent image features so as to increase the adaptable work surfaces.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A tracking device including an image sensor, a light source and a processor is provided. The image sensor senses reflected light or scattered light formed by the light source illuminating a work surface. The processor calculates a trace of the tracking device according to one of the reflected light and the scattered light that generates more apparent image features so as to increase the adaptable work surfaces.

Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower insulating structure disposed over a lower dielectric structure surrounding an interconnect. The lower insulating structure has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure, a data storage structure is disposed on first interior sidewalls and an upper surface of the bottom electrode, and a top electrode is disposed on second interior sidewalls and an upper surface of the data storage structure. An interconnect via is on an upper surface of the top electrode. A bottom surface of the bottom electrode is laterally outside of a bottom surface of the interconnect via.

Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.

Abstract: An opening structure of a tool grip includes a left grip and a right grip that are intersected and pivoted. An elastic connecting strap is provided between the left and right grips. The left grip has at least two left studs. The right grip has at least two right studs. The connecting strap has a length greater than a distance between the left and right grips. One end of the connecting strap has at least two left recessed portions for engagement of the left studs. Another end of the connecting strap has at least two right recessed portions for engagement of the right studs. By selecting the position where the left recessed portions are engaged with the left studs and the position where the right recessed portions are engaged with the right studs, a force that the connecting strap pushes against the left and right grips to open is adjustable.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A hand tool structure has two plier bodies pivoted by a pivot member, and a knob mechanism for controlling opening and closing of the two plier bodies. The pivot member includes a cylindrical body pivoted to the two plier bodies and a spring sleeved onto the cylindrical body and having two ends abutting against the two plier bodies. Opposing sides of the two plier bodies each include a V- shaped groove to form a square clamping hole when the two plier bodies are closed; a row of teeth; a first cutting portion for cutting an electric wire or cable; a second cutting portion for cutting a metal wire; a wavy peeling portion for peeling a jacket of the electric wire, the peeling portion including curved sections each having a different radius of curvature, wherein when the two plier bodies are closed, the curved sections form receiving holes with different diameters.

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

Abstract: An opening structure of a tool grip includes a left grip and a right grip that are intersected and pivoted. An elastic connecting strap is provided between the left and right grips. The left grip has at least two left studs. The right grip has at least two right studs. The connecting strap has a length greater than a distance between the left and right grips. One end of the connecting strap has at least two left recessed portions for engagement of the left studs. Another end of the connecting strap has at least two right recessed portions for engagement of the right studs. By selecting the position where the left recessed portions are engaged with the left studs and the position where the right recessed portions are engaged with the right studs, a force that the connecting strap pushes against the left and right grips to open is adjustable.

Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.