SEMICONDUCTOR DEVICE

Abstract

The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. application Ser. No. 14/251,765, filed on Apr. 14, 2014, and entitled “SEMICONDUCTOR DEVICE”, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The instant disclosure relates to a semiconductor device; in particular, to a semiconductor device with self-aligned isolation trenches.

2. Description of Related Art

Dynamic random access memory (DRAM) is an electronic data storage device. In DRAM, each bit of binary data is stored in a tiny circuit called a memory cell consisting of a transistor and a capacitor. Generally, the better operating capability of computer software becomes, the greater memory capacitance of computer hardware need. Thus, the method for manufacturing DRAM capacitors is now an indispensable technology.

With the vigorous development of semiconductor industry, the dimension of integrated circuit elements nowadays range from micron size to submicron size. For DRAM, that is to say the cross-sectional area of each capacitor and each gap between capacitors become smaller. The traditional method for patterning the target layer on the substrate comprises the following steps. A photoresist material is spin-coated on the target layer in the first place. The photoresist material is exposed and developed through a patterned mask to form a patterned photoresist layer in the second place. Further, a process of etching is conducted to pattern the target layer by using the patterned photoresist layer as the etch mask.

However, in view of the resolution of pattern transfer is increased and the critical dimension of the line width is reduced. Limitation exists for improving lithography by only optical improvement.

In addition, MIM (Metal insulator Metal) capacitors basically a parasitic capacitor between the metal layers. Generally three or more reticles are used in the processing steps. In order to overcome its complex process, the design of DRAM will focus on a reduction in the number of reticles used.

SUMMARY OF THE INVENTION

The object of the instant disclosure is to provide a semiconductor device with self-aligned isolation trenches for reducing the reticle requirements as well as accurately place well-defined isolation trenches in the semiconductor substrate.

In order to achieve the aforementioned objects, according to an embodiment of the instant disclosure, a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.

Based on the above, because the buried bit lines and the isolation trenches can be formed in the semiconductor substrate, the semiconductor device (i.e. DRAM device) having 4F² size can be achieved. Moreover, the buried bit lines and the isolation trenches are formed via a self-aligned process which is used to substitute the lithography process. In other words, the buried bit lines and the isolation trenches can be accurately placed in the semiconductor substrate without any reticle. Hence, the instant method can reduce the reticle requirements to reduce the processing cost.

In order to further appreciate the characteristics and technical contents of the instant disclosure, references are hereunder made to the detailed descriptions and appended drawings in connection with the instant disclosure. However, the appended drawings are merely shown for exemplary purposes, rather than being used to restrict the scope of the instant disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a process flow diagram of a method for manufacturing semiconductor device according to an embodiment of the instant disclosure;

FIG. 1A shows a process flow diagram of a method for forming buried bit lines and insulating structures according to an embodiment of the instant disclosure;

FIGS. 2-7 are cross-sectional diagrams illustrating the processing steps of method for manufacturing semiconductor device according to an embodiment of the instant disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the instant disclosure. Other objectives and advantages related to the instant disclosure will be illustrated in the subsequent descriptions and appended drawings.

The instant disclosure relates to a semiconductor device with a novel structural semiconductor substrate. Said semiconductor device not only can accurately place well-defined isolation trenches without any reticle, but also can help improve the alignment of the landing areas of capacitors and bit line contacts and buried bit line trenches. Hence, the yield rate of DRAM modules can be increased.

Please refer to FIG. 1 as well as FIGS. 2-7. FIG. 1 is a process diagram of the method for manufacturing semiconductor device. FIGS. 2-7 are cross-sectional diagrams illustrating the processing steps of the method. Following will describe the method for manufacturing semiconductor device. Thus, the instant disclosure can be performed by any person skilled in the art when understanding its features. Basically, the method comprises the following steps:

Step 10 is providing a semiconductor substrate 1 defined a plurality of active areas AA thereon. Referring to FIG. 2, the step S11 further comprises, but not limited to, providing a substrate S, then sequentially forming a pad layer 11, a first mask layer 12, and a second mask layer 13 on the substrate S.

In practice, the substrate S can be a silicon substrate or any other suitable substrate. The pad layer 11 is made of oxide (pad oxide layer) or nitride (pad nitride layer). The first mask layer 12 and the second mask layer 13 are made of, but not limited to, silicon nitride and polysilicon respectively. In addition, the material of the first or second mask layers 12, 13 can be selected based on the etch selectivity either. For example, the material of the first or second mask layers 12, 13 is selected from the group consisting of silicon nitride, silicon oxide, and polysilicon.

Referring to FIG. 1A as well as FIGS. 3-5, step S12 is forming at least two buried bit lines 2a in each of the active areas AA and an insulating structure 2b disposed above and opposite to the at least two buried bit line 2a. It is notable that the step S12 is a key step of the instant disclosure. Concretely speaking, the step S12 further comprises, but not limited to, the following steps. First, a process of deposition is conducted to form a blocking layer 21 over the second mask layer 13, and a process of partial etch is then conducted to pattern the blocking layer 21 to define a plurality of bit line areas BL (step S121). Specifically, each of the bit line areas BL is among and vertically overlapped with each of the active areas AA. Second, another process of deposition is conducted to form a sacrificial layer 22 that conformally covers the patterned blocking layer 21 (step S122). That is, the sacrificial layer 22 can define a plurality of first openings 220 therein, and the first openings 220 are among the bit line areas BL respectively.

Third, still another process of deposition is conducted to form a masking material over the patterned blocking layer 21 and fill the first openings 220, then a process of etch is conducted remove a portion of the masking material outside the first openings 220 to form a plurality of masking structures 23, and then a process of etch back is conducted to etch each of the masking structures 23 to have a desired thickness (step S123). Fourth, another process of partial etch is conducted to selectively remove the sacrificial layer 22, the second mask layer 13, the first mask layer 12, the pad layer 11, and the substrate S in order with the patterned blocking layer 21 and the masking structures 23 as self-aligned masks to form two bit line trenches 10a in each of the bit line areas BL (step S124).

After that, the masking structures 23 and the remained sacrificial layer 22 are completely removed, and still another process of partial etch id conducted to selectively remove the second mask layer 13 with the patterned blocking layer 21 as mask to form a plurality of second openings 130 (step S125). Specifically, each of the second openings 130 is opposite to the two bit line trenches 10a. Finally, a dielectric body 24 is formed to fill each of the second openings 130 and the corresponding two bit line trenches 10a (step S126). Consequently, there are two buried bit lines 2a in each of the bit line areas BL, and there is an insulating structure 2b disposed above and opposite to the at least two buried bit lines 2a.

In the step S120, the blocking layer 21 can be made of oxide rich material, and be patterned via a selective etch process. That is to say, a patterned photoresist layer (not shown) is formed to partially cover the surface of the blocking layer 21 in the first place. A process of etch is conducted to pattern the blocking layer 21 through the patterned photoresist layer in the second place. In the step S121, the sacrificial layer 22 can be made of silicon rich material such as silicon nitride, and be formed along topography via atomic layer deposition (ALD). In this way, the thickness of the sacrificial layer 22 can be controlled at sub-micron level, and the uniformity of the sacrificial layer 22 can be improved. In the step S122, the masking structures 23 can be made of silicon rich material either.

Consequently, in the step S123, a portion of the sacrificial layer 22 made of silicon rich material and the semiconductor substrate 1 can be removed via a plasma etching process or a reactive ion etching process with the patterned blocking layer 21 and the masking structures 23 as self-aligned masks to form the bit line trenches 10a without any reticle. Specifically, the etching gas can be selected to exhibit high selectivity for silicon such as the mixing gas of HBr and O₂. Thus, over-etching effect on the other layer can be prevented in the etching process.

Referring to FIG. 6, step S14 is forming a self-aligned spacer 3 on the sidewalls of each of the insulating structures 2b. It is notable that the step S13 is another key step of the instant disclosure. In practice, the self-aligned spacers 3 can be made of silicon nitride, silicon oxide, or silicon carbon. Concretely speaking, the step S13 further comprises, but not limited to, the following steps. A spacer material (not shown) is conformally deposited over the semiconductor substrate 1 in the first place. Further, a process of etch back is performed on the spacer material to form the self-aligned spacers 3 to partially expose the surface of the semiconductor substrate 1.

Referring to FIG. 7, step S16 is selectively removing the semiconductor substrate 1 with the self-aligned spacers 3 as masks to form a plurality of isolation trenches 10b that isolate the buried bit lines 2a in different active areas AA. Most importantly, the landing areas of capacitor and bit line contact C, BLC are defined while the formation of the isolation trenches 10b. For each active area AA, a landing area of bit line contact BLC is positioned between two buried bit lines 2a. Moreover, two landing areas of capacitor are positioned between each of the two buried bit lines 2a and the adjacent isolation trench 10b. Specifically, the dimension of each landing area of capacitor C can be adjusted according to the thickness of each self-aligned spacer 3.

Please refer to FIGS. 6 and 7 again, the technical features of the method for manufacturing semiconductor device are mentioned above. So the instant disclosure further relates to a semiconductor device which includes a semiconductor substrate 1, a plurality of buried bit lines 2a, a plurality of insulating structures 2b, and a plurality of self-aligned spacers 3.

In this embodiment, the semiconductor substrate 1 has a plurality of active areas AA defined thereon. The buried bit lines 2a are disposed in the semiconductor substrate 1, wherein two of the buried bit lines 2a are positioned in each of the active areas AA. The insulating structures 2b are disposed on the semiconductor substrate 1, wherein each of the insulating structures 2b is positioned on and opposite to the two of the buried bit lines 2a. The self-aligned spacers 3 are disposed on the sidewalls of the insulating structures 2b respectively to partially expose the surface of the semiconductor substrate 1. By the way, the processing steps for forming the semiconductor substrate 1, the buried bit lines 2a, the insulating structures 2b, and the self-aligned spacers 3 are mentioned above. No attention is given to said processing steps.

Based on above, the semiconductor device, in comparison with the traditional one, has the following advantages.

Firstly, because the buried bit lines and the isolation trenches can be formed in the semiconductor substrate, the semiconductor device (i.e. DRAM device) having 4F² size can be achieved. Moreover, the buried bit lines and the isolation trenches are formed via a self-aligned process which is used to substitute the lithography process. In other words, the buried bit lines and the isolation trenches can be accurately placed in the semiconductor substrate without any reticle. Hence, the semiconductor device can reduce the reticle requirements to reduce the processing cost.

Further, the isolation trenches are formed through the self-aligned spacers. Thus, the semiconductor device not only can be easily manufactured by using a simple process, but also can prevent the offset of the landing areas of capacitor due to the misalignment of reticle or the smaller dimension. In this way, the yield rate of the semiconductor device can be increased, and the semiconductor device can be miniaturized.

Furthermore, the dimension of the landing areas of capacitor in the semiconductor device can easily controlled by setting the process parameters, and the uniformity of the subsequently formed capacitors can be improved.

The descriptions illustrated supra set forth simply the preferred embodiments of the instant disclosure; however, the characteristics of the instant disclosure are by no means restricted thereto. All changes, alternations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the instant disclosure delineated by the following claims.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate defined a plurality of active areas thereon;

a plurality of buried bit lines disposed in the semiconductor substrate, wherein at least two of the buried bit lines are positioned in each of the active areas;

a plurality of insulating structures disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the at least two of the buried bit lines; and

a plurality of self-aligned spacers disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a substrate, a pad layer disposed on the substrate, a first mask layer disposed on the pad layer, and a second mask layer disposed on the first mask layer.

3. The semiconductor device according to claim 2, wherein the pad layer is made from oxide or nitride.

4. The semiconductor device according to claim 2, wherein the first mask layer is made from silicon nitride, silicon oxide, or polysilicon, and the second mask layer is made from silicon nitride, silicon oxide, or polysilicon.

5. The semiconductor device according to claim 2, wherein the semiconductor substrate has a plurality self-aligned isolation trenches that pass through the second mask layer, the first mask layer, and the pad layer by a dry-etch process with the self-aligned spacers as masks.

6. The semiconductor device according to claim 1, wherein each of the self-aligned spacers with a predetermined width is configured to define a vertically overlapped capacitor landing area, and the at least two of the buried bit lines in every active area are configured to define a vertically overlapped bit line contact area therebetween.

7. The semiconductor device according to claim 5, wherein each of the capacitor landing areas has a width equal to the maximum width of the corresponding self-aligned spacer.

8. The semiconductor device according to claim 1, wherein each of the self-aligned spacers is made from silicon oxide, silicon nitride, or silicon carbide.