Abstract: A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

Abstract: A method for fabricating a silicon oxide/silicon nitride/silicon oxide stacked layer structure is described. A bottom oxide layer is formed over a substrate. A surface treatment is then performed on the first silicon oxide layer to form an interface layer over the bottom oxide layer. The surface treatment is conducted in a nitrogen ambient. Thereafter, a silicon nitride layer is formed over the interface layer, followed by forming an upper silicon oxide layer over the silicon nitride layer.

Abstract: In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.

Abstract: In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.

Abstract: A method of fabricating a flash memory. A tunneling dielectric layer and a conductive layer are formed on a substrate. The conductive layer is patterned to form a floating gate. A source/drain region is formed in the substrate between the floating gates. A gate dielectric layer is formed. The gate dielectric layer includes an oxide layer formed on the floating gate by in-situ steam generation (ISSG). A control gate is formed on the gate dielectric layer.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: The method for improving the performance of flash memory. A substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate, structure are formed on the tunnel oxide layer. The gate structure including a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO layer on the floating gate, a second polysilicon layer as a control gate on the interpoly dielectric layer. Moreover, the poly stringer is exit between the gates, wherein the poly stringer is unmovied after etched. Next, the oxygen free radical process cell oxidation is processed. The results ONO encroachment is very slightly then improvement of 6% GCR with pre-mixing gas process cell oxidation can increase operation speed by more than 5 times and eliminated poly stringer.

Abstract: A method for scaling down thickness of ONO film with remote plasma nitridation, the method includes the acts of forming a substrate; form a first oxide layer on the substrate; nitrogenizing the oxide layer under the ONO film to form a nitridation layer; forming a nitride layer on the nitridation layer; and forming a second oxide layer on the nitride layer.

Abstract: A method for forming a tunnel oxide film of a flash memory. A chamber having a wafer therein is provided. Hydrogen and oxygen are introduced into the chamber, whereby the chamber has a pressure and a temperature therein. The pressure of the chamber is decreased to about 5-15 torrs. The temperature of the chamber is increased to about 850° C. to about 1100° C., whereby the hydrogen reacts with the oxygen to form a plurality of oxygen radicals, and whereby the oxygen radicals react with the wafer to form a silicon oxide film.