Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract: A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.

Abstract: A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract: A high dielectric antenna substrate includes a first dielectric layer having a first dielectric constant, and a second dielectric layer having a second dielectric constant. The second dielectric layer is formed on one surface of the first dielectric layer. The second dielectric constant is lower than the first dielectric constant. Furthermore, a first metal layer and a second metal layer are optionally formed on the same surface or two surfaces of the first dielectric layer to compose a capacitor.

Abstract: A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.

Abstract: An adjustable resistor embedded in a multi-layered substrate and method for forming the same. The adjustable resistor comprises: a planar resistor, having a plurality of terminals; and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network, wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is varied and thus the resistance value of the adjustable resistor can be precisely adjusted.

Abstract: The invention relates to a high frequency inductor device with high quality factor (Q). The inductor device comprises a substrate and a gradually sized conductive coil with a plurality of windings surrounded and disposed on the substrate. The windings comprises a first conductive segment disposed on a first surface of the substrate, a second conductive segment disposed on a second surface of the substrate, a first conductive via hole connecting the first and second conductive segments, and a second conductive via hole connecting the second conductive segment to a first conductive segment of the following winding. The length of the first conductive segment is different than that of the first conductive segment of the following winding.

Abstract: A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.

Abstract: A resistor structure embedded in a multi-layer circuit board and manufacturing method thereof are provided. Resistive material is coated on any layer among the multi-layer circuit board, and two symmetric electrodes are formed in the geometric center of the resistive material area. The two electrodes are disposed in the resistive material layer and are covered by the resistive material. And the two electrodes are led out from respective bores at the central position of the resistive electrodes, for connecting to any other metal layer. This resistor structure can avoid the unstable resistance when the coated resistor is operated at high frequency, and also avoid the formation untrimmed edges during coating that affects the precision of resistance.

Abstract: A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

Abstract: Embedded inductor devices and fabrication methods thereof. An embedded inductor device includes a substrate, a conductive coil disposed on the substrate, and a patterned high-permeability (?r>1) magnetic layer on the substrate. The patterned high-permeability (?r>1) magnetic layer physically contacts the conductive coil. The conductive coil and the patterned high-permeability (?r>1) magnetic layer are intersected and substantially perpendicular to each other.

Abstract: Embedded inductor devices and fabrication methods thereof. An embedded inductor device includes a substrate, a conductive coil disposed on the substrate, and a patterned high-permeability (?r>1) magnetic layer on the substrate. The patterned high-permeability (?r>1) magnetic layer physically contacts the conductive coil. The conductive coil and the patterned high-permeability (?r>1) magnetic layer are intersected and substantially perpendicular to each other.

Abstract: A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

Abstract: A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.