Abstract: A balanced-to-unbalanced transformer embedded with a filter, the balanced-to-unbalanced transformer being disposed in a multi-layered substrate and comprising vertically coupled transmission lines designed in different layers in the multi-layer substrate to increase transmission performances. A capacitor and a transmission line are connected to a single-ended I/O port of the balanced-to-unbalanced transformer such that a filter is embedded in the balanced-to-unbalanced transformer.

Abstract: A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

Abstract: A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.

Abstract: A vertical complementary fractal antenna is provided, which includes a first fractal structure and a second fractal structure. The first fractal structure is defined as a superposition over at least one iteration of a motif, while the second fractal structure has a pattern complementary to that of the first fractal structure. Thus, the antenna may effectively increase bandwidth.

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract: The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.

Abstract: A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.

Abstract: A high frequency and wide band impedance matching via is provided. As an application to multi-layer printed circuit boards, for example, the multi-layer circuit board has several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers are sited on different circuit layers, and each signal transmission trace is opposite to one of the ground layers. The signal transmission vias are connected between the signal transmission traces. The ground vias are connected between the ground layers. The ground vias are opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias are sited to stabilize the characteristic impedance of the transmission traces.

Abstract: A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to an unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract: A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to a unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.

Abstract: An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.

Abstract: The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract: An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.