Abstract: A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

Abstract: A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

Abstract: A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2), having an input circuit to which the input signal (in) may be applied and an output circuit at which the output signal (out) may be picked off, the input circuit having at least one native transistor.

Abstract: A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) into an output signal (out) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2). An input circuit (1) receives the input signal and an output circuit (2) provides the output signal (out), where the input circuit includes a parallel circuit made up by a first cascode circuit and a second cascode circuit, and the first and second cascode circuits each being formed by a first transistor in the source circuit and a second transistor in the gate circuit, a dynamic control being provided for the second transistors.

Abstract: The invention relates to a level slider circuit having a first level slider (1) and a second level slider (2) switched in series for the conversion of an input signal (Vin) from a first operating voltage range (A) at a first ground voltage (VSSA) and a first supply voltage (VDDA) into an output signal (Vout) in a second operating voltage range (B) at a second ground voltage (VSSB) and a second supply voltage (VDDB), wherein the first level slider (1) is embodied for the conversion of the input signal (Vin) to the ground voltage (VSSA) of the second operating voltage range (B) for the conversion of the input signal (Vin), and that the second level slider (2) is embodied for the conversion of an intermediate signal (VZ) output by the first level slider (1) to the output signal travel (?Vout).

Abstract: A CMOS output stage operates in A/B push-pull mode and is driven with a control potential (ud) from a preamplifier stage via a control line (st). The control line (st) feeds the gate terminals of a complementary transistor pair (kt), the first transistor (n1) of which is used as first push-pull output transistor and the second transistor (p1) of which is connected to the gate terminal of a second push-pull output transistor (pa) via a current balancing arrangement. The source terminal of the first and of the second transistor (n1, p1) is connected to a first and, respectively, to a second fixed potential (u1, u2), the second fixed potential (u2) being stabilised in a low-impedance manner by an active compensation circuit (K).

Abstract: The invention relates to an amplifier circuit provided with offset reduction and with a sufficiently high bandwidth, having two input stages of a first amplifier connected in parallel at the input terminals, wherein the first input stage is connected directly to the input terminals, and the second input stage is connected through a second amplifier, and wherein a third amplifier is connected at the output of the first amplifier, wherein the second amplifier is provided with a symmetrical load.

Abstract: An integrated audio amplifier includes an operation amplifier that includes a precharging device and a monitoring device. The operation amplifier further comprises an input stage and an output stage. The output stage includes a compensation capacitor. The precharging device is configured to precharge the compensation capacitor to a voltage that can be predetermined. The monitoring device detects a not-ready-for operation state of the audio amplifier and activates the precharging device, while at the same time, the output stage is blocked until such time as the compensation capacitor is charged by the precharging device to the predetermined voltage.

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: To suppress oscillation modes, in particular, higher-order oscillation modes, in a ring oscillator comprising delay elements forming the oscillator ring and being linked by nodes in the ring, and further comprising a gate element located in the oscillator ring which is activated by a control signal to open and close the gate element, the control signal is derived from at least one of the levels of the oscillator signal at the nodes. The control signal is such that the normal oscillation mode, that is, the fundamental oscillation and/or another desired higher-order oscillation, is not affected by the gate. However, unwanted oscillation modes (e.g., the higher oscillation modes) are effectively suppressed in the case of the fundamental oscillation representing the normal oscillation mode.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: To detect a fault state due to a line break in power supply lines on the receiving side during the operation of a transducer device, the transducer output voltage is forced to an extreme voltage range by a co-integrated p-channel-depletion-transistor. As a result, the signal detection device can reliably detect the presence of the fault state due to a line break in the supply feed lines.

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C1), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V1) is present at a voltage divider that includes a resistor (R2) and a circuit section (R1) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R1) is realized as a switched capacitor (C1), and the resistance (R2) is realized as an MOS transistor (T1).

Abstract: A two-stage amplifier includes a first stage and a second stage that are DC-connected through a coupling capacitor Cp. A charge pump generates a bias voltage Vp that is applied across the coupling capacitor Cp leads to maintain the time average of the voltage across said coupling capacitor constant.

Abstract: A function generator includes a switching stage for forming a defined signal waveform. The switching stage includes switching transistors that are turned on in a predetermined sequence of undelayed and delayed clock signals, with an output node summing the output currents of the switching transistors. The function generator also includes a delay device that generates the undelayed and delayed clock signals from an applied clock signal. The delays of the delayed clock signals define predetermined instants within at least one period of the applied clock signal. The switching edge is divided into different time ranges whose respective edge steepnesses are adjustable independently of each other. By point-mirroring the signal waveform about a medium value of the signal edge, frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency are reduced.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

Abstract: A monolithic integrated sensor circuit is disclosed comprising a sensor system for generating an electronic sensor signal; a supply unit for the sensor system; an amplifying stage for amplifying the sensor signal; a plurality of inverting devices in the signal path of the amplifying stage which reverse the polarity of the sensor signal at equal time intervals, the time intervals and inversion of the sensor signal being controlled by a clock signal source; and an averaging combiner stage whose input receives an amplified sensor signal and whose output has a reference polarity which is controlled by means of the inverting devices in such a way as to be always the same regardless of the switching state in the signal path. The monolithic integrated sensor circuit of the present invention minimizes the offset error.