Abstract: A current switch for use in digital-to-analog converters having high dynamic accuracy includes first and second electronic switches, the first of which connects either a constant-current source or a constant-current sink to an output terminal. The output terminal is connected to a low-pass filter. When the constant-current source is connected to the output terminal, the second switch connects the constant-current sink to a reference-voltage source. When the constant current sink is connected to the output terminal, the second electronic switch connects the constant current source to the reference-voltage terminal. This antiphase switching of the two electronic switches is controlled by a control circuit to which a clocked signal and a clock signal are applied. The clocked signal is, for example, a pulse-density-modulated signal which appears as a demodulated signal at the output of the low-pass filter.

Abstract: A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.

Abstract: To avoid interference signals caused by overlapping edges of a switching signal for driving p-channel-transistor/n-channel-transistor pairs, a drive circuit contains a first series combination of the current paths of a first p-channel transistor, a first n-switching transistor, and a first n-channel transistor and a second series combination of a second p-channel transistor, a second n-switching transistor and a second n-channel transistor, with the gate of the first p-channel transistor connected to the current-path junction of the second series combination, and the gate of the second p-channel transistor connected to the current-path junction of the first series combination. The switching signal and the inverse thereof are applied to the gates of the first n-channel transistor and the second n-channel transistor, respectively. The gates of the n-switching transistors are presented with the n-clock.

Abstract: A monolithic integrated digital-to-analog converter makes use of rotating current-source control (dynamic element matching). After the conversion of a digital input signal into a code containing a sequence of first binary conditions corresponding to the numerical value of the input signal (so-called thermometer code), the bit switches of possibly same-sized current sources are rotatingly controlled in the sense of being selected, so that it becomes possible in the manufacture of the monolithic integrated digital-to-analog converters to balance out the manufacturing tolerances or process variations of the current sources.