Abstract: The invention relates to a digitally adjustable crystal oscillator having a quartz crystal and a monolithic integrated oscillator circuit including a series combination of a first frequency-adjusting capacitor C1 and a second frequency-adjusting capacitor C2 connected in parallel with the quartz crystal and comprising parallel-connected first capacitance stages and parallel-connected second capacitance stages, respectively, and an inverter circuit connected in parallel with the quartz crystal and comprising a feedback resistor R.sub.K, the output of the innverter circuit being connected to a load resistor. The inverter circuit comprises parallel-connected inverter stages, and switching elements are provided within the inverter stages and cqapacitor stages in such a way that a respective one of the inverter stages as well as a first capacitance stage C.sub.1i and a second capacitance stage C.sub.2i are switchable into or out of circuit by means of a control signal I.sub.i.

Abstract: A monolithic integrable mixer network for a mixer console includes a variable gain preamplifier for each sound channel, a summing amplifier whose summing gain is adjustable differently for each sound channel, and a control unit which divides the channel gain for the respective sound channel between the preamplifier and the summing amplifier according to a ratio dependent on the desired channel gain to optimize the noise performance of the mixer network.

Abstract: A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

Abstract: A current mirror circuit including at least one current bank transistor coupled to a cascade transistor. The cascade transistor further coupled to a current mirror input. A current-controlled current source operable for both receiving a differential current from said current mirror input and for producing a charging current for charging a gate of the at least one current bank transistor in order to null the differential current.

Abstract: The invention relates to a magnetic-field sensor with a Hall effect device, a power supply, and an evaluating facility, which can be supplied with a Hall signal from the Hall-effect device and comprises an input amplifier, a storage element, and a signal superposition unit. To improve the accuracy of the magnetic-field sensor, in a first phase, a balancing signal for balancing the measurement-signal path with respect to an interface can be produced with the evaluating facility, the balancing signal being storable in the storage element, and in a second phase, the balancing signal stored in the storage element can be applied through the signal superposition unit to the interface, where it is superimposed on a Hall signal.

Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, the

Abstract: A voltage regulator contains a reference which provides a value for comparison by an error amplifier which generates a control signal in response to the deviation of the output to the reference. As many stages of the circuit as possible are connected to fixed potential points. The fixed potential points are fixed with respect to the regulated output voltage. This provides a voltage regulator which is insensitive to interference signals from the unregulated supply voltage. The interference signals from the supply voltage are further buffered by using relatively small capacitors within the circuit, rather than a large external filter means.

Abstract: A voltage regulator in the form of a series regulator for generating a regulated supply voltage includes a control loop with a reference network, a difference device, and a control element. The control element is connected between a first terminal and a second terminal. The power supply for the reference network and the difference device is coupled to the second terminal. During a starting phase, a starting device with an auxiliary circuit pulls the control loop into the regular operating range.

Abstract: The present invention is a monolithic integrated differential amplifier having an operational amplifier and a digitally controlled means for setting the gain of said differential amplifier wherein the gain is adjustable by means of a resistive feedback network formed by a resistor chain whose taps are coupled via a multiplexer to the operational amplifier. The operational amplifier in the present invention is designated as an adaptive amplifier because its gain-bandwidth product is digitally adjustable in steps, with the respective gain-bandwidth product selected being adapted to the gain setting of the monolithic integrated differential amplifier.

Abstract: The present invention is a circuit for regulating the current across an impedance load. This current regulating circuit is comprised of a main current path including a first control path, a reference-current path including a similar, second control path, and a control means including a pulse generator, a current source controller and an operational amplifier for controlling the first and second control paths in parallel.

Abstract: A circuit and method automatically compensate a monolithic integrated Hall sensor having a Hall element therein, wherein a device for generating operating currents is technologically and thermally tightly coupled with the Hall element. The production-induced and temperature-induced variations in the sensitivity of the Hall element are compensated for by a defined control of the supply current and the offset current. For the control, the thermal and technological parameters of the Hall element semiconductor region or equivalent regions in corresponding circuits are used. For this purpose, at least two current sources are provided which generate at least two auxiliary currents with different temperature dependences. By means of adding/subtracting devices, resultant currents with other temperature dependences are formed from the auxiliary currents by summation/subtraction and different weighting.

Abstract: A CMOS transconductance amplifier with a floating operating point which has low quiescent-current consumption for a voltage-to-current converter. On the other hand, the current yield of the output transistor in an output current mirror for a load current is high. The low quiescent-current consumption is achieved by connecting a coupling transistor used as a low-impedance diode in parallel with an active load in the current output stage of the voltage-to-current converter. The high current yield is achieved by means of a positive-feedback circuit which adds to the quiescent current of the voltage-to-current converter an auxiliary current proportional to the load current, thus forming a floating operating point.

Abstract: A CMOS circuit for averaging digital-to-analog converters includes a shift register of series-connected master and slave cells controlled by a shift clock. The input of the shift register is supplied with a pulse-density-modulated data signal, and the outputs of each of the master and slave cells are connected to a data-dependent control input of a multistage gate circuit. The gate circuits are controlled by a gate clock and cause constant currents to be switched via two buses to the input and output of a p-channel current mirror in accordance with the state of the master or slave cell. The input of a current mirror is constantly supplied with one-half the sum current of the constant-current sources, and the current mirror provides current scaling, preferably by a factor of 0.5.

Abstract: A class-AB push-pull CMOS output stage is driven over a control line with a drive potential from an input stage. The control line feeds the gate terminals of a complementary transistor pair whose first transistor serves as a first push-pull output transistor and whose second transistor is connected to the gate terminal of a second push-pull output transistor via a current-mirror arrangement. The source terminals of the first and second transistors are tied to a first fixed potential and a second fixed potential, respectively, the latter being stabilized by a low-impedance active compensation circuit.

Abstract: A transconductance amplifier is driven by a difference voltage which is coupled through a first input terminal to a first voltage-to-current converter and through a second input terminal to a second voltage-to-current converter of identical design. An identical third voltage-to-current converter has its input terminal connected to the tap of a resistive voltage divider which is connected between the first and second input terminals. The output signal of the transconductance amplifier can be taken from the current outputs of the first and second voltage-to-current converters. The current outputs have a difference current which is proportional to the value of the difference voltage.

Abstract: An offset-voltage-balancing operation amplifier for difference signals includes an auxiliary and a main amplifier, each having a difference input and an auto-zero input. To provide offset balancing, the auto-zero inputs are connected to the potentials of two integrated storage capacitors. The difference input of the auxiliary amplifier can be short-circuited via first and second switching means, and the two storage capacitors are connected to the output of the auxiliary amplifier via third and fourth switching means. The sensitivity of the auto-zero inputs is less than the sensitivity of the difference inputs.

Abstract: In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.

Abstract: A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.

Abstract: In this protective arrangement, a resistor between a pad (p) and a transistor to be protected is implemented with an expansion region (e) which lies completely below the pad (p) and extends beyond the latter along the entire circumference of the pad. An elongate region (z) extends along the circumference of the expansion region (e) and is connected to circuit ground via an interconnection track (b). The connection between the elongate region (z) and the interconnection track (b) has a low resistance.

Abstract: To a prior art CMOS full-adder stage having sixteen transistors, a static inverter is added which consists of a P-type transistor and an N-type transistor, and the series combination (sc) of P- and N-type transistors is wired symmetrically. This increases the processing frequency, because the carry-signal path is no longer loaded by the four transistors contributing to the summation.