Patents by Inventor Ulrich Weiss
Ulrich Weiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8086657Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: GrantFiled: April 9, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Patent number: 7865758Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: June 16, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Patent number: 7761726Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: May 7, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Patent number: 7667504Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.Type: GrantFiled: March 11, 2008Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Florian Braun, Dedric Lichtenau, Thomas Pflueger, Ulrich Weiss
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Patent number: 7487377Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: GrantFiled: February 9, 2005Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Publication number: 20090021288Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.Type: ApplicationFiled: March 11, 2008Publication date: January 22, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Florian Braun, Cedric Lichtenau, Thomas Pflueger, Ulrich Weiss
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Publication number: 20080294706Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: ApplicationFiled: April 9, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Publication number: 20080247342Abstract: The invention relates to a method and a device for setting up a connection between a terminal (MS) in a communication network and a network element (AS, IPU) in an IP network for exchanging data of an IP-based service. The invention is characterized by setting up a connection between at least one network unit (OSUS-Proxy) of the communication network and the terminal (MS) of the communication network for exchanging data of an IP-based service comprising at least one signaling message. The at least one network unit (OSUS-Proxy) of the communication network, in accordance with the content of the at least one signaling message by the terminal (MS), sets up a connection for exchanging data of an IP-based service with the network element (AS, IPU) of the IP network with at least one recipient-specific signaling.Type: ApplicationFiled: June 20, 2005Publication date: October 9, 2008Applicant: Siemens AktiengesellschaftInventors: Martin Gugerell, Heinrich Huber, Erwin Postman, Ulrich Weiss
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Publication number: 20080244300Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: ApplicationFiled: June 16, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Publication number: 20080215906Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: ApplicationFiled: May 7, 2008Publication date: September 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Patent number: 7406495Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.Type: GrantFiled: October 26, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
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Patent number: 7308592Abstract: The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.Type: GrantFiled: February 11, 2005Date of Patent: December 11, 2007Assignee: International Business Machines CorporationInventors: Dietmar Schmunkamp, Andreas Wagner, Tobias Webel, Ulrich Weiss
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Patent number: 7296610Abstract: A method of manufacturing metallic components consisting of at least two different materials, one of them being an iron-based alloy and the other an aluminum-based alloy, and involving the steps of: depositing a metallic layer onto the body made from the iron-based alloy, said layer being an aluminum-based alloy, preferably based on Al—Si or Fe, placing the coated body in a casting mold and casting an aluminum-based alloy about the coated body. Prior to placing the body in the casting mold, the metallic layer of the body is sprayed and/or blasted with silicon powder and/or Borax (Na2B4O7—10H2O, hydrated sodium borate).Type: GrantFiled: March 15, 2004Date of Patent: November 20, 2007Assignee: Ford Global Technologies, LLCInventors: Matthew Zaluzec, David Cook, Ulrich Weiss, Maik Broda, Clemens Verpoort
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Patent number: 7260494Abstract: A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.Type: GrantFiled: February 11, 2005Date of Patent: August 21, 2007Assignee: International Business Machines CorporationInventor: Ulrich Weiss
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Publication number: 20060195287Abstract: A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.Type: ApplicationFiled: February 11, 2005Publication date: August 31, 2006Applicant: International Business Machines CorporationInventor: Ulrich Weiss
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Publication number: 20060184814Abstract: The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Inventors: Dietmar Schmunkamp, Andreas Wagner, Tobias Webel, Ulrich Weiss
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Publication number: 20060179364Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Scott Swaney, Kenneth Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
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Publication number: 20060143896Abstract: A method of manufacturing metallic components consisting of at least two different materials, one of them being an iron-based alloy and the other an aluminum-based alloy, and involving the steps of: depositing a metallic layer onto the body made from the iron-based alloy, said layer being an aluminum-based alloy, preferably based on Al—Si or Fe, placing the coated body in a casting mold and casting an aluminum-based alloy about the coated body. Prior to placing the body in the casting mold, the metallic layer of the body is sprayed and/or blasted with silicon powder and/or Borax (Na2B4O7—10H2O, hydrated sodium borate).Type: ApplicationFiled: March 15, 2004Publication date: July 6, 2006Inventors: Matthew Zaluzec, David Cook, Ulrich Weiss, Maik Broda, Clemens Verpoort
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Publication number: 20060097814Abstract: A method of sideband suppression for an I/Q modulator as well as an electronic circuit for sideband suppression, a transceiver, a base station and a mobile station making use of the electronic circuit in the framework of wireless telecommunication and digital communication networks. The inventive method of sideband suppression is based on a two step modulation scheme, where a baseband signal is modulated by means of two modulators to an intermediate frequency signal, which in turn is modulated to a RF signal by means of an analog I/Q modulator. The invention provides adaptive and dynamic tuning of the phase of the intermediate frequency signal, preferably by making use of two CORDIC modules as modulators that are driven by a phase accumulator. Additionally, a control unit serves to tune the phase of the intermediate frequency signal in response to detect an undesired sideband signal in the RF output of the I/Q modulator.Type: ApplicationFiled: October 24, 2005Publication date: May 11, 2006Inventors: Heinz Schlesinger, Ulrich Weiss
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Patent number: 6989696Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.Type: GrantFiled: November 19, 2003Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Rolf Hilgendorf, Jens Kuenzer, Cédric Lichtenau, Thomas Pflueger, Mathew I. Ringler, Gerard M. Salem, Peter A. Sandon, Dana J. Thygesen, Ulrich Weiss