Abstract: An integrated circuit includes a first set and a second set of scan flip flops, a circuit under test, and a controller. Each scan flip flop of the first set includes a scan enable input coupled to a first scan enable signal. The circuit under test includes logic elements downstream of the first set. The second set includes at least one scan flip flop downstream of the logic elements. Each scan flip flop of the second set includes a scan enable input coupled to a second scan enable signal. The controller is configured to test the logic elements by shifting test patterns into the first set while asserting both the first and second scan enable signal, launching the test patterns, and capturing results from the second set while continuing to assert the first scan enable signal and deasserting the second scan enable signal.

Abstract: According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: A computer-implemented method, according to one approach, includes: determining whether a destination for a domain name system (DNS) query corresponds to an existing source network address translation (SNAT) port in response to receiving the DNS query. In response to determining that the destination for the DNS query corresponds to an existing SNAT port, the DNS query is modified to incorporate the existing SNAT port. A map entry corresponding to the existing SNAT port is also updated, and the modified DNS query is satisfied. Other systems, methods, and computer program products are described in additional approaches.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

Abstract: The Walnut Healthcare Global System Creative tools increase health literacy and reduce healthcare costs by discovering the drivers of spending and spending growth in US healthcare. The system involves multi-talented groups of people and Artificial Intelligence Technology working together to achieve better results by making more precise healthcare decisions. Lifelong educational offerings that develop management competencies and improve professional skills are vital to success through these tools. Increased healthcare use and intensity of services have been the key drivers of healthcare spending growth as the US population continues to age, with healthcare costs rising at all levels. The third eye is also known as self-power to see things through the inner eye in the art and creative environment. It is part of the creative tools called “the subtle body,” which aids the tools to see things through force in the body that moves and sees things through the inner eye.

Abstract: A flame stabilization apparatus with fuel injection upstream of a torpedo, includes a flame stabilization plate that incorporates spokes that stabilize a flame over a range of operations of a burner. The spokes surrounds a fuel plenum with respect to the burner. A first group of fuel ports can be located in a fuel tube upstream of the torpedo and a second group of fuel ports can be located in the flame stabilization plate. A discharge cone includes a discharge zone for the burner, wherein the flame with respect to the flue gas is stabilized at an end of the burner in the discharge zone.

Abstract: A refractory apparatus may include a refractory bock comprising a heat shield. The refractory block can include a group of flue gas ports that acts as a gateway for flue gas produced due to combustion downstream of a burner. A suction created in the burner drives the flue gas into the burner through the flue gas ports. A group of staged risers can be housed within the refractory block. The staged risers are protected in staged fuel riser housings in the refractory block. A discharge cone is located in the refractory block for flame stabilization in the burner.

Abstract: A printed circuit board (PCB), including: a processing unit; a plurality of layers; and a plurality of vias, each via extending through two or more of the layers, wherein a first via of the plurality of vias has a first pad at a first layer of the plurality of layers and a second via of the plurality of vias has a second pad at the first layer of the plurality of layers, wherein the first pad is conjoined with the second pad to form a first heatsink at the first layer that dissipates heat away from the processing unit.

Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

Abstract: A fuel-fired burner includes a combustion air inlet for receiving combustion air coupled to a combustion air nozzle at an input to a second chamber within a burner housing spaced apart from a third chamber within the second chamber. The combustion air nozzle directs the combustion air into the third chamber. A fuel inlet coupled to a burner nozzle secured to a burner mounting plate has a recycle port for receiving hot exhaust gas provided to an exhaust gas path. A jet pump located entirely inside the burner housing is configured to receive the hot exhaust gas from the exhaust gas path. The jet pump operates by flowing the combustion air through the combustion air nozzle which suctions in the hot exhaust gas through the recycle port into the exhaust gas path then into a gas mixing zone for mixing the hot exhaust gas and the combustion air.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may measure at least one of a first height value and a first width value of a first eye diagram of a first signal; measure at least one of a second height value and a second width value of a second eye diagram of a second signal; determine at least one of a height difference value and a width difference value respectively between the at least one of the first height value and the first width value of the first eye diagram and the at least one of the second height value and the second width value of the second eye diagram; and determine that the at least one of the height difference value and the width difference value respectively meets or exceeds a height threshold value or a width threshold value.

Abstract: A fuel-fired burner 100 includes a combustion air inlet 113 for receiving combustion air coupled to a combustion air nozzle 136 at an input to a second chamber 152 within a burner housing 110 spaced apart from a third chamber 168 within the second chamber. The combustion air nozzle 136 directs the combustion air 171 into the third chamber 168. A fuel inlet 111 coupled to a burner nozzle 167 secured to a burner mounting plate 161 has a recycle port 164 for receiving hot exhaust gas provided to an exhaust gas path 165. A jet pump located entirely inside the burner housing is configured to receive the hot exhaust gas from the exhaust gas path. The jet pump operates by flowing the combustion air through the combustion air nozzle 136 which suctions in the hot exhaust gas through the recycle port into the exhaust gas path then into a gas mixing zone 178 for mixing the hot exhaust gas and the combustion air.

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

Abstract: A zoned dielectric loss circuit board system includes a board. A first differential trace is included in the board. A dielectric layer is included the board and that includes a first dielectric layer zone that engages the first differential trace and that includes first dielectric loss characteristics, and a second dielectric layer zone that is located immediately adjacent the first dielectric layer zone and that includes second dielectric loss characteristics that are greater than the first dielectric loss characteristics. A second differential trace may be included in the board in engagement with the second dielectric layer zone, and may have a second trace length that is shorter than a first trace length of the first differential trace.

Abstract: A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

Abstract: A printed circuit board (PCB), including: a processing unit; a plurality of layers; and a plurality of vias, each via extending through two or more of the layers, wherein a first via of the plurality of vias has a first pad at a first layer of the plurality of layers and a second via of the plurality of vias has a second pad at the first layer of the plurality of layers, wherein the first pad is conjoined with the second pad to form a first heatsink at the first layer that dissipates heat away from the processing unit.