Patents by Inventor Umesh Chandra

Umesh Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10396760
    Abstract: A differential pair contact resistance asymmetry compensation system includes a board with a differential trace pair. A receiver device is coupled to the differential trace pair via a receiver device connector interface, and a transmitter device is coupled to the differential trace pair via a transmitter device connector interface. The transmitter device transmits a contact resistance compensation data stream to the receiver device via the differential trace pair. The transmitter device then adjusts an impedance provided by the transmitter device to compensate for a contact resistance asymmetry in the transmitter device connector interface. When the transmitter device determines that differential trace pair signal transmission capabilities for the differential trace pair in transmitting the contact resistance compensation data stream have improved in response to the adjustment of the impedance provided by the transmitter device, it sets the impedance provided by the transmitter device.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 27, 2019
    Assignee: Dell Poducts L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Hamza S. Rahman
  • Publication number: 20190239339
    Abstract: A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Mallikarjun Vasa
  • Patent number: 10352996
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Publication number: 20190208632
    Abstract: A circuit board assembly of an information handling system has stepped diameter vias that carry communication signals through printed circuit board (PCB) substrates. Each stepped diameter via has a first barrel portion of a first diameter that is drilled through a first portion of the PCB substrates and that is at least lined with a conductive material to electrically conduct a selected one of: (i) a direct current and (ii) a communication signal from an outer layer to an internal layer of the more than one PCB substrate. Each stepped diameter via further includes a second barrel portion that extends from the first barrel portion deeper into the PCB substrates. The second barrel portion has a second diameter that is less than the first diameter and the smaller second diameter improves signal integrity (SI).
    Type: Application
    Filed: January 4, 2018
    Publication date: July 4, 2019
    Inventors: UMESH CHANDRA, BHYRAV M. MUTNURY, MALLIKARJUN VASA
  • Publication number: 20190162768
    Abstract: A test apparatus includes a host compliance printed circuit board having a first circuit plane and a second circuit plane separated by at least one dielectric layer. A first row of surface mount pads are disposed on the first circuit plane. The first row of surface mount pads includes a first pad and a second pad. A second and third row of surface mount pads are disposed on the first circuit plane. A first and second differential pair of circuit lines is disposed on the first circuit plane. The first differential circuit line has one end coupled to the first pad. The second differential circuit line has one end coupled to the second pad. The first and second differential pair of circuit lines extend from the first and second pads and between the second and third rows of surface mount pads.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventor: UMESH CHANDRA
  • Publication number: 20190166687
    Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10299370
    Abstract: A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: May 21, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury
  • Patent number: 10103910
    Abstract: A PAM equalization optimization system includes a BIOS coupled to a PAM engine and an equalization engine. The BIOS determines an effective equalization tap number of equalization taps that each provide an equalization result above a predetermined amount. The BIOS then determines whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number of equalization taps that are available for equalizing a signal. When the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-symbol equalization on signals modulated using the PAM engine. When the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-bit equalization on signals modulated using the PAM engine.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 16, 2018
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Arun Reddy Chada, Han Deng
  • Patent number: 9936572
    Abstract: A differential trace pair system includes a board having a first board structure member and a second board structure member. A differential trace pair in the board includes a first differential trace pair portion of a first width outside the board structure, and a second differential trace pair portion of a second width extending through the board structure. A first outer edge and a second outer edge of the second differential trace pair portion define the second width that is less than the first width. A first board structure member channel is defined by the first outer edge adjacent the first board structure member, a second board structure member channel is defined by the second outer edge adjacent the second board structure member and the first and second board structure member channels provide a third width of the second differential trace pair portion that is less than the second width.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: April 3, 2018
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Henry M. Wolst
  • Publication number: 20170147967
    Abstract: This disclosure relates generally to inventory management, and more particularly to allocating pallet locations to items in a distribution center. In one embodiment, the method includes receiving an input including an item identifier. Based on the item identifier, a load distribution information is accessed. Based on the load distribution information associated with the item and one or more allocation parameters associated with the one or more pallet locations, one or more pallet locations from amongst a plurality of pallet locations are determined. The one or more allocation parameters are indicative of the availability of pallets at the one or more pallet locations in real-time. At least one pallet location is selected from amongst the one or more pallet locations based on a location identifier associated with the at least one location, for accommodating the item. The location identifier is indicative of prioritization of the pallet location for accommodating the item.
    Type: Application
    Filed: February 9, 2016
    Publication date: May 25, 2017
    Applicant: Tata Consultancy Services Limited
    Inventors: Umesh Chandra BEHERA, Ajay Bansal
  • Publication number: 20170059656
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Patent number: 9551746
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: January 24, 2017
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Publication number: 20170013716
    Abstract: A differential trace pair system includes a board having a first board structure member and a second board structure member. A differential trace pair in the board includes a first differential trace pair portion of a first width outside the board structure, and a second differential trace pair portion of a second width extending through the board structure. A first outer edge and a second outer edge of the second differential trace pair portion define the second width that is less than the first width. A first board structure member channel is defined by the first outer edge adjacent the first board structure member, a second board structure member channel is defined by the second outer edge adjacent the second board structure member and the first and second board structure member channels provide a third width of the second differential trace pair portion that is less than the second width.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 12, 2017
    Inventors: Umesh Chandra, Henry M. Wolst
  • Publication number: 20160366805
    Abstract: The present invention relates to the development of a novel, morphologically and genetically distinct khusinol rich essential oil producing clone of vetiver [Vetiveria zizaniodes (L.) Nash. syn. Chrysopogon zizanioides (L.) Roberty; family Poacaeae} named ‘CIMAP-Khusinolika’. The plant of this clone is characterized by spreading type clump canopy in the initial stage, white feathery stigma and capable of producing >1% (v/w) essential oil containing 45-50% Khusinol (v/v) obtained after hydro-distillation from fresh roots harvested from 6 month old plantations. This clone has unique ISSR profiles that serve as DNA-fingerprints. The clone was obtained through recurrent selection in polycrossed population generated from the bulk of wild collection, and can be propagated through vegetative slips (3 to 6 month old stem with few roots) for commercial plantation as a short duration crop.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Harmesh Singh Chauhan, Hemendra Pratap Singh, Chandan Singh Chanotiya, Ajit Kumar Shasany, Umesh Chandra Lavania, Virendra Kumar Singh Tomar, Alok Kalra, Ashok Kumar Singh
  • Publication number: 20160266204
    Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 15, 2016
    Inventors: Umesh Chandra, Timothy Thinh Mai
  • Patent number: 9385974
    Abstract: A communication system transfers user data messages to users. The system stores the user data messages in association with message stream identifiers and message delivery metrics. The system processes the message delivery metrics to enter the user data messages into a plurality of delivery queues associated with multiple message transmission systems. The system receives a data request indicating a message stream identifier and a message transmission system, and in response, identifies a message set and associated delivery metrics. The system receives a data instruction indicating new delivery metrics, and in response, re-enters the message set into the delivery queue. The communication system transfers the user data messages based on their associated delivery queues over data networks for receipt by the users.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 5, 2016
    Assignee: Sprint Communications Company L.P.
    Inventors: Umesh Chandra Upadhyay, Robin Dale Katzer, Geoff A. Holmes, Robert H. Burcham
  • Publication number: 20160117429
    Abstract: A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Rahul Jain, Nitin Dhamija, Umesh Chandra Lohani
  • Patent number: 9317639
    Abstract: A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rahul Jain, Nitin Dhamija, Umesh Chandra Lohani
  • Patent number: PP26474
    Abstract: The present invention relates to the development of a novel clone of Vetiver [Vetveria zizaniodes (L) Nash. syn. Chrysopogon zizaniodes (L.) Roberty; family Poaceae], named ‘CIMAP-KHUS 40’ characterised by somatic chromosome number 4x=40, larger stomata, fast growing deep penetrating roots, and seed infertility disabling its spread as a weed. This clone has unique ISSR and RAPD profiles that serve as DNA-fingerprints, and is developed from a unique diploid plant (2n=20). The invention document details all the pertinent data relating to this clone, its biological features and usefulness, and the method of its development.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 8, 2016
    Assignee: Council of Scientific and Industrial Research
    Inventors: Umesh Chandra Lavania, Santosh Kumar Rai, Seshu Lavania, Surochita Basu, Basant Kumar Dubey, Ram Ujagir
  • Patent number: PP28388
    Abstract: The present invention relates to the development of a novel, morphologically and genetically distinct khusinol rich essential oil producing clone of vetiver [Vetiveria zizaniodes (L.) Nash. syn. Chrysopogon zizanioides (L.) Roberty; family Poacaeae} named ‘CIMAP-Khusinolika’. The plant of this clone is characterized by spreading type clump canopy in the initial stage, white feathery stigma and capable of producing >1% (v/w) essential oil containing 45-50% Khusinol (v/v) obtained after hydro-distillation from fresh roots harvested from 6 month old plantations. This clone has unique ISSR profiles that serve as DNA-fingerprints. The clone was obtained through recurrent selection in polycrossed population generated from the bulk of wild collection, and can be propagated through vegetative slips (3 to 6 month old stem with few roots) for commercial plantation as a short duration crop.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: September 12, 2017
    Assignee: Council of Scientific and Industrial Research
    Inventors: Harmesh Singh Chauhan, Hemendra Pratap Singh, Chandan Singh Chanotiya, Ajit Kumar Shasany, Umesh Chandra Lavania, Virendra Kumar Singh Tomar, Alok Kalra, Ashok Kumar Singh