Patents by Inventor Umesh Mishra

Umesh Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050242366
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 3, 2005
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20050214992
    Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.
    Type: Application
    Filed: May 6, 2005
    Publication date: September 29, 2005
    Inventors: Arpan Chakraborty, Benjamin Haskell, Stacia Keller, James Speck, Steven Denbaars, Shuji Nakamura, Umesh Mishra
  • Patent number: 6949774
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf), and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: September 27, 2005
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20050077541
    Abstract: A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), deposited on the substrate, an AlGaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded AlGaN layer deposited on the AlGaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded AlGaN layer to a top of the n-type doped graded AlGaN layer, and a cap layer, comprised of GaN or AlGaN with an Al mole fraction smaller than that of the AlGaN barrier layer, deposited on the n-type doped graded AlGaN layer.
    Type: Application
    Filed: October 12, 2004
    Publication date: April 14, 2005
    Inventors: Likun Shen, Sten Heikman, Umesh Mishra
  • Publication number: 20050067716
    Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.
    Type: Application
    Filed: October 29, 2004
    Publication date: March 31, 2005
    Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
  • Publication number: 20050051800
    Abstract: A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.
    Type: Application
    Filed: May 28, 2004
    Publication date: March 10, 2005
    Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
  • Publication number: 20050040385
    Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11{overscore (2)}0) a-plane GaN layers are grown on an r-plane (1{overscore (1)}02) sapphire substrate using MOCVD. These non-polar (11{overscore (2)}0) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.
    Type: Application
    Filed: April 15, 2003
    Publication date: February 24, 2005
    Inventors: Michael Craven, Stacia Keller, Steven Denbaars, Tal Margalith, James Speck, Shuji Nakamura, Umesh Mishra
  • Patent number: 6849882
    Abstract: A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an AlyGa1?yN (y=1 or y 1) layer on the GaN buffer layer. An AlxGa1?xN (0?x?0.5) barrier layer on to the AlyGa1?yN layer, opposite the GaN buffer layer, AlyGa1?yN layer having a higher Al concentration than that of the AlxGa1?xN barrier layer. A preferred AlyGa1?yN layer has y=1 or y˜1 and a preferred AlxGa1?xN barrier layer has 0?x?0.5. A 2DEG forms at the interface between the GaN buffer layer and the AlyGa1?yN layer. Respective source, drain and gate contacts are formed on the AlxGa1?xN barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the AlyGa1?yN layer and a nucleation layer between the AlxGa1?xN buffer layer and the substrate.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: February 1, 2005
    Assignee: Cree Inc.
    Inventors: Prashant Chavarkar, Ioulia P. Smorchkova, Stacia Keller, Umesh Mishra, Wladyslaw Walukiewicz, Yifeng Wu
  • Publication number: 20050006669
    Abstract: A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals.
    Type: Application
    Filed: August 11, 2004
    Publication date: January 13, 2005
    Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
  • Publication number: 20040080010
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Application
    Filed: May 20, 2003
    Publication date: April 29, 2004
    Applicant: Cree Lighting Company
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20030062525
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf, and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Application
    Filed: June 6, 2002
    Publication date: April 3, 2003
    Applicant: Cree Lighting Company
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20030020092
    Abstract: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD).
    Type: Application
    Filed: July 23, 2002
    Publication date: January 30, 2003
    Inventors: Primit Parikh, Umesh Mishra, Yifeng Wu
  • Publication number: 20030015708
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Application
    Filed: July 23, 2001
    Publication date: January 23, 2003
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20020167023
    Abstract: A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an AlyGa1−yN (y=1 or y 1) layer on the GaN buffer layer. An AlxGa1−xN (0≦x≦0.5) barrier layer on to the AlyGa1−yN layer, opposite the GaN buffer layer, AlyGa1−yN layer having a higher Al concentration than that of the AlxGa1−xN barrier layer. A preferred AlyGa1−yN layer has y=1 or y≃1 and a preferred AlxGa1−xN barrier layer has 0≦x≦0.5. A 2DEG forms at the interface between the GaN buffer layer and the AlyGa1−yN layer. Respective source, drain and gate contacts are formed on the AlxGa1−xN barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the AlyGa1−yN layer and a nucleation layer between the AlxGa1−xN buffer layer and the substrate.
    Type: Application
    Filed: March 19, 2002
    Publication date: November 14, 2002
    Applicant: CREE LIGHTING COMPANY and REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Prashant Chavarkar, Ioulia P. Smorchkova, Stacia Keller, Umesh Mishra, Wladyslaw Walukiewicz, Yifeng Wu