Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1?M3; M1?M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.

Abstract: System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network 320) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure 215) that can controllably electrically couple two outputs.

Abstract: A power management system (12) in an electronic device (10). The system comprises circuitry (14x), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CPx). The system alternatively or cumulatively also comprises circuitry (22x) for indicating a potential capability of operational speed of the data path and/or circuitry (24x) for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry (26) for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.

Abstract: A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3; M1-M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A domino logic circuit includes a precharge device precharging a precharge node during a precharge phase and a logic block receiving plural input signals to conditionally discharge the precharge node. In this improvement a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node.

Abstract: The power consumption of a single chip data processing device (21) is controlled. An activity meter (53) signals the activity level of at least one functional unit (FU). A clock arbiter (51) has three states: an up state; a hold state; and a down state. The clock arbiter progresses from the up state to the hold state and from the hold state to the down state when the activity level is below a predetermined activity threshold. The clock arbiter progresses from the down state to the hold state and from the hold state to the up state when the activity level is above the predetermined activity threshold. A clock generating circuit (43, 45, 47) supplies a clock signal periodically increasing in frequency responsive to the up state, unchanging in frequency responsive to the hold state and periodically decreasing in frequency responsive to the down state.

Abstract: This invention concerns power consumption control of memory having a fully powered state and at least one lower power state. The invention changes the memory to the fully powered state upon receipt of a memory access request. This memory access request is serviced in the fully powered state. The memory is returned to a lower power state after expiration of a grace period following a last memory access request. This grace period can be measured by a predetermined time or a predetermined number of memory access requests or a combination of these factors. The predetermined time may be fixed in manufacture or programmable in operation via a control register or data stored in a predetermined set of address locations within the address space of the memory. This invention is useful in portable electronic devices such as wireless telephones.

Abstract: This invention involves logic circuits formed of metal oxide semiconductor field effect transistors having differing threshold voltages. In a first embodiment, the logic circuit includes a first and a second series connection. The first series connection between a first supply voltage and an output node consists of a source-drain path of an N-channel transistor having a high threshold voltage and a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a low threshold voltage. The second series connection between said supply voltage and said output node consists of a source-drain path of a P-channel transistor having the high threshold voltage and a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having the low threshold voltage. The two high threshold voltage MOSFETs receive at their respective gates inverse signals so that either both are conducting or both are off.

Abstract: This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage current of LVT transistors. A two input multiplexer includes two transmission gates driven in opposite phases by a selection control signal. One transmission gate, preferably the transmission gate most often selected, includes LVT transistors while the other transmission gate includes HVT transistors. A hybrid threshold voltage D flip-flop circuit employs LVT transistors in input transmission gates of both a master latch and a slave latch. In a conventional circuit, the output invertor of the slave latch also includes LVT transistors. In a split slave dual path circuit, the intermediate inverter also includes LVT transistors.

Abstract: A D flip-flop circuit has two current paths supply the output signal of this flip-flop. A push-pull circuit including an inverter and a transmission gate clocked in a first phase supplies the output of the D flip-flop in a first output path. A slave latch connected to the transmission gate having an output clocked in a second phase opposite to the first phase serves as the second path to the output. In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch. The master latch may include a feedback P-type MOSFET. The slave latch may includes two slave latch inverters and a transmission gate clocked in the second phase connected to the output of the D flip-flop output. In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate.

Abstract: This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage current of LVT transistors. A two input multiplexer includes two transmission gates driven in opposite phases by a selection control signal. One transmission gate, preferably the transmission gate most often selected, includes LVT transistors while the other transmission gate includes HVT transistors. A hybrid threshold voltage D flip-flop circuit employs LVT transistors in input transmission gates of both a master latch and a slave latch. In a conventional circuit, the output invertor of the slave latch also includes LVT transistors. In a split slave dual path circuit, the intermediate inverter also includes LVT transistors.

Abstract: A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates.

Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5). A first inverter (5526) is connected between first supply voltage (3.3v) and ground and has a first inverter input (IN) and a first inverter output. A second inverter (5518) is connected between second supply voltage (5v) and ground and has a second inverter input (INT) and a second inverter output (OUT). A first feedback transistor (5520) has connections to the second supply voltage (5v), and to the second inverter input (INT) and the second inverter output (OUT). A second feedback transistor (5524) has connections to ground, and to the second inverter input (INT) and the second inverter output (OUT). First and second open-type inverters (5522, 5528) are connected to ground and each of the open-type inverters has an input and output.

Abstract: The present invention provides a method for transferring groups of data between a microprocessor cache memory (114) and an external memory (105) across a data bus (Bbus). Each group of data includes as many bits of data as the width of the bus (Bubs) with the total amount of data transferred filling a line in the cache memory (114). The bus interface unit (112) of the microprocessor (110) initiates a burst read by starting a read request, asserting the address strobe bit and sending the initial requested address on the external bus address bits of the microprocessor (110). The external system will then respond by asserting a burst ready signal, followed by the data bits residing in the appropriate address position. The particular addresses for this data is selected according to the current burst mode, which may be high performance, low power or compatible with a previously known burst mode.