Patents by Inventor Uri Frodis

Uri Frodis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080121343
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 16, 2008
    Publication date: May 29, 2008
    Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
  • Publication number: 20080105355
    Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 8, 2008
    Inventors: Ananda Kumar, Ezekiel Kruglick, Adam Cohen, Kieun Kim, Gang Zhang, Richard Chen, Christopher Bang, Vacit Arat, Michael Lockard, Uri Frodis, Pavel Lembrikov, Jeffrey Thompson
  • Publication number: 20080093424
    Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 24, 2008
    Inventors: Ananda Kumar, Ezekiel Kruglick, Adam Cohen, Kieun Kim, Gang Zhang, Richard Chen, Christopher Bang, Vacit Arat, Michael Lockard, Uri Frodis, Pavel Lembrikov, Jeffrey Thompson
  • Publication number: 20080050524
    Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.
    Type: Application
    Filed: April 9, 2007
    Publication date: February 28, 2008
    Inventors: Ananda Kumar, Jorge Albarran, Adam Cohen, Kieun Kim, Michael Lockard, Uri Frodis, Dennis Smalley
  • Patent number: 7271888
    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: September 18, 2007
    Assignee: Microfabrica Inc.
    Inventors: Uri Frodis, Adam L. Cohen, Michael S. Lockard
  • Publication number: 20060108678
    Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
    Type: Application
    Filed: June 30, 2005
    Publication date: May 25, 2006
    Inventors: Ananda Kumar, Ezekiel Kruglick, Adam Cohen, Kieun Kim, Gang Zhang, Richard Chen, Christopher Bang, Vacit Arat, Michael Lockard, Uri Frodis, Pavel Lembrikov, Jeffrey Thompson
  • Publication number: 20050230261
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: October 20, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Patent number: 6951456
    Abstract: A generally toroidal counterflow heat exchanger is the main element of a combustor that operates at a micro scale. The combustor includes a central combustion region with openings to a reactant gas channel and an exhaust gas channel. The reactant channel and exhaust channels are coiled around each other in a spiral configuration that reduces heat loss. An electric current microgenerator is similar and also includes a thermoelectric active wall composed of n-type and p-type thermoelectric elements as part of a channel wall of the microcombustor. The thermoelectric active wall includes fins configured to increase the temperature differential across the thermoelectric elements relative to the temperature difference between the thermoelectric elements and the reactant and exhaust gases. A method of monolithically fabricating such microdevices by electrodepositing multiple layers of material is also provided.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 4, 2005
    Assignee: University of Southern California
    Inventors: Adam L. Cohen, Paul D. Ronney, Uri Frodis, Lars Sitzki, Eckart H. Meiburg, Steffen Wussow
  • Publication number: 20050215046
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: September 29, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Publication number: 20050199583
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: September 15, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Publication number: 20050202180
    Abstract: Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g.
    Type: Application
    Filed: January 3, 2005
    Publication date: September 15, 2005
    Inventors: Adam Cohen, Uri Frodis, Michael Lockard, Ananda Kumar, Gang Zhang, Dennis Smalley
  • Publication number: 20050194258
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: September 8, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Publication number: 20050181316
    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
    Type: Application
    Filed: January 3, 2005
    Publication date: August 18, 2005
    Inventors: Uri Frodis, Adam Cohen, Michael Lockard
  • Publication number: 20050173374
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: August 11, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Publication number: 20050176238
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Application
    Filed: January 3, 2005
    Publication date: August 11, 2005
    Inventors: Adam Cohen, Michael Lockard, Kieun Kim, Qui Le, Gang Zhang, Uri Frodis, Dale McPherson, Dennis Smalley
  • Publication number: 20050142846
    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
    Type: Application
    Filed: January 3, 2005
    Publication date: June 30, 2005
    Inventors: Uri Frodis, Adam Cohen, Michael Lockard
  • Publication number: 20050072454
    Abstract: A generally toroidal counterflow heat exchanger is the main element of a combustor that operates at a micro scale. The combustor includes a central combustion region with openings to a reactant gas channel and an exhaust gas channel. The reactant channel and exhaust channels are coiled around each other in a spiral configuration that reduces heat loss. An electric current microgenerator is similar and also includes a thermoelectric active wall composed of n-type and p-type thermoelectric elements as part of a channel wall of the microcombustor. The thermoelectric active wall includes fins configured to increase the temperature differential across the thermoelectric elements relative to the temperature difference between the thermoelectric elements and the reactant and exhaust gases. A method of monolithically fabricating such microdevices by electrodepositing multiple layers of material is also provided.
    Type: Application
    Filed: July 29, 2003
    Publication date: April 7, 2005
    Inventors: Adam Cohen, Paul Ronney, Uri Frodis, Lars Sitzki, Eckart Meiburg, Steffen Wussow
  • Publication number: 20050023145
    Abstract: Numerous electrochemical fabrication methods and apparatus are provided for producing multi-layer structures (e.g. having meso-scale or micro-scale features) from a plurality of layers of deposited materials using adhered masks (e.g. formed from liquid photoresist or dry film), where two or more materials may be provided per layer where at least one of the materials is a structural material and one or more of any other materials may be a sacrificial material which will be removed after formation of the structure. Materials may comprise conductive materials that are electrodeposited or deposited in an electroless manner. In some embodiments special care is undertaken to ensure alignment between patterns formed on successive layers.
    Type: Application
    Filed: May 7, 2004
    Publication date: February 3, 2005
    Inventors: Adam Cohen, Jill Thomassian, Michael Lockard, Marvin Kilgo, Uri Frodis, Dennis Smalley
  • Patent number: 6613972
    Abstract: A generally toroidal counterflow heat exchanger is the main element of a combustor that operates at a micro scale. The combustor includes a central combustion region with openings to a reactant gas channel and an exhaust gas channel. The reactant channel and exhaust channels are coiled around each other in a spiral configuration that reduces heat loss. An electric current microgenerator is similar and also includes a thermoelectric active wall composed of n-type and p-type thermoelectric elements as part of a channel wall of the microcombustor. The thermoelectric active wall includes fins configured to increase the temperature differential across the thermoelectric elements relative to the temperature difference between the thermoelectric elements and the reactant and exhaust gases. A method of monolithically fabricating such microdevices by electrodepositing multiple layers of material is also provided.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 2, 2003
    Assignee: University of Southern California
    Inventors: Adam L. Cohen, Paul Ronney, Uri Frodis, Lars Sitzki, Eckart Meiburg, Steffen Wussow
  • Publication number: 20010029974
    Abstract: A generally toroidal counterflow heat exchanger is the main element of a combustor that operates at a micro scale. The combustor includes a central combustion region with openings to a reactant gas channel and an exhaust gas channel. The reactant channel and exhaust channels are coiled around each other in a spiral configuration that reduces heat loss. An electric current microgenerator is similar and also includes a thermoelectric active wall composed of n-type and p-type thermoelectric elements as part of a channel wall of the microcombustor. The thermoelectric active wall includes fins configured to increase the temperature differential across the thermoelectric elements relative to the temperature difference between the thermoelectric elements and the reactant and exhaust gases. A method of monolithically fabricating such microdevices by electrodepositing multiple layers of material is also provided.
    Type: Application
    Filed: January 5, 2001
    Publication date: October 18, 2001
    Inventors: Adam L. Cohen, Paul Ronney, Uri Frodis, Lars Sitzki, Eckart Meiburg, Steffen Wussow