Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract: In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.

Abstract: In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.

Abstract: A method for enhancing a process and profile simulator algorithm predicts the surface profile that a given plasma process will create. An energetic particle is first tracked. The ion fluxes produced by the energetic particle are then recorded. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.

Abstract: In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.

Abstract: A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed thereon. The method also includes forming a conformal layer of polymer over the photoresist mask and a portion of the semiconductor substrate not covered by the photoresist mask while concurrently removing a portion of the conformal layer of polymer. The thickness of the conformal layer of polymer on each region of the semiconductor substrate is set to vary depending on a removal rate of the conformal layer of polymer in each region of the semiconductor substrate.

Abstract: An apparatus configured to remove chamber deposits between process operations is provided. The processing chamber includes a top electrode in communication with a power supply. A processing chamber defined within a base, a sidewall extending from the base, and a top disposed on the sidewall is provided. The processing chamber has an outlet enabling removal of fluids within the processing chamber. The processing chamber includes a substrate support and an inner surface of the processing chamber defined by the base, the sidewall and the top. The inner surface is coated with a fluorine containing polymer coating. The fluorine containing polymer coating is configured to release fluorine upon creation of an oxygen plasma in the processing chamber to remove a residue deposited on the fluorine containing polymer coating. The residue was deposited on the polymer coating from a processing operation performed in the processing chamber.

Abstract: A method for enhancing a process and profile simulator algorithm predicts the surface profile that a given plasma process will create. An energetic particle is first tracked. The ion fluxes produced by the energetic particle are then recorded. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.

Abstract: An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

Abstract: A plasma in a vacuum chamber where a workpiece is processed is bounded by a plasma confinement volume including a region between a first electrode simultaneously responsive to power at first and second RF frequencies and a DC grounded second electrode. A DC grounded extension is substantially aligned with the first electrode. A substantial percentage of power at the first frequency is coupled to a path including the first and second electrodes but not the extension while a substantial percentage of power at the second frequency is coupled to a path including the first electrodes and extension, but not the second electrode. Changing the relative powers at the first and second frequencies, as applied to the first electrode, controls DC bias voltage of the first electrode.

Abstract: A method for removing chamber deposits in between process operations in a semiconductor process chamber is provided. The method initiates with depositing a fluorine containing polymer layer over an inner surface of a semiconductor process chamber where the semiconductor chamber is empty. Then, a wafer is introduced into the semiconductor process chamber after depositing the fluorine containing polymer layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the fluorine containing polymer layer covering the inner surface of the semiconductor process chamber. Then, the wafer is removed from the semiconductor process chamber. Next, an oxygen based cleaning operation is performed. The oxygen based cleaning operation liberates fluorine from the fluorine containing polymer layer to remove a silicon based residue. An apparatus configured to remove chamber deposits between process operations is also provided.

Abstract: A method enhances a process and profile simulator algorithm to predict the surface profile that a given plasma process will create. The method first tracks an energetic particle and then records the ion fluxes produced by the energetic particle. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.

Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract: A method for removing chamber deposits in between process operations in a semiconductor process chamber is provided. The method initiates with depositing a fluorine containing polymer layer over an inner surface of a semiconductor process chamber where the semiconductor chamber is empty. Then, a wafer is introduced into the semiconductor process chamber after depositing the fluorine containing polymer layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the fluorine containing polymer layer covering the inner surface of the semiconductor process chamber. Then, the wafer is removed from the semiconductor process chamber. Next, an oxygen based cleaning operation is performed. The oxygen based cleaning operation liberates fluorine from the fluorine containing polymer layer to remove a silicon based residue. An apparatus configured to remove chamber deposits between process operations is also provided.

Abstract: A plasma in a vacuum chamber where a workpiece is processed is bounded by a plasma confinement volume including a region between a first electrode simultaneously responsive to power at first and second RF frequencies and a DC grounded second electrode. A DC grounded extension is substantially aligned with the first electrode. A substantial percentage of power at the first frequency is coupled to a path including the first and second electrodes but not the extension while a substantial percentage of power at the second frequency is coupled to a path including the first electrodes and extension, but not the second electrode. Changing the relative powers at the first and second frequencies, as applied to the first electrode, controls DC bias voltage of the first electrode.

Abstract: A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer comprised of polymer material and a portion of the patterned photoresist mask are then removed. The layer comprised of polymer material is preferably formed by introducing a process gas into a plasma environment and is preferably formed with less thickness in a low aspect ratio area relative to a high aspect ratio area.

Abstract: An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

Abstract: A method scales plasma process settings from a first processing device to a second processing device. The first processing device has a first geometry and a first set of process parameters. The second processing device has a second geometry and a second set of process parameters. A first set of plasma process settings that generates the first set of process parameters of the first processing device having the first geometry is determined. The first set of plasma process settings is reduced to isolate at least one variable on which the first set of plasma process settings depends on for each plasma process setting. A scaling factor is calculated for each plasma process setting from the first set of plasma process settings such that the first set of process parameters substantially equals the second set of process parameters.

Abstract: A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed thereon. The method also includes forming a conformal layer of polymer over the photoresist mask and a portion of the semiconductor substrate not covered by the photoresist mask while concurrently removing a portion of the conformal layer of polymer. The thickness of the conformal layer of polymer on each region of the semiconductor substrate is set to vary depending on a removal rate of the conformal layer of polymer in each region of the semiconductor substrate.

Abstract: A method and an apparatus for a semi-empirical process simulation using a calibrated profile simulator to create a reactor model which can predict neutral and ion flux distributions on a substrate as a function of the reactor settings include providing a set of conditions characterized by unique reactor settings. Wafers are processed under each condition. Etch or deposition rates and surface profiles are measured and used in the calibrated profile simulator to derive the flux distributions. The flux distributions data generated by the processes are then used to create a reactor model.