Patents by Inventor Valery M. Dubin
Valery M. Dubin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220059484Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
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Patent number: 11201129Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: February 22, 2019Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
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Publication number: 20190198472Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: February 22, 2019Publication date: June 27, 2019Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
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Patent number: 10249588Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: December 5, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
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Patent number: 10035147Abstract: An embodiment of the invention relates to a wafer comprising a plurality of biochips and interconnects on the wafer, the biochip comprising a biochip pad, a synthesis electrode and a gel comprising a probe, wherein a plurality of the biochip pads of the plurality of the biochips are interconnected by the interconnects to carry out a chemical reaction on a plurality of the synthesis electrodes.Type: GrantFiled: December 31, 2014Date of Patent: July 31, 2018Assignee: Intel CorporationInventors: Valery M. Dubin, Nikolay Suetin
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Publication number: 20170084564Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: ApplicationFiled: December 5, 2016Publication date: March 23, 2017Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
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Patent number: 9543261Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: December 20, 2010Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
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Patent number: 9508675Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.Type: GrantFiled: August 22, 2013Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
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Publication number: 20150231633Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.Type: ApplicationFiled: December 31, 2014Publication date: August 20, 2015Inventors: Valery M. Dubin, Nikolay Suetin
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Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
Patent number: 9085461Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.Type: GrantFiled: May 16, 2012Date of Patent: July 21, 2015Assignee: INTEL CORPORATIONInventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett -
Publication number: 20150096894Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
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Patent number: 8940143Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.Type: GrantFiled: June 29, 2007Date of Patent: January 27, 2015Assignee: Intel CorporationInventors: Valery M. Dubin, Nikolay Suetin
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Patent number: 8911609Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.Type: GrantFiled: April 20, 2012Date of Patent: December 16, 2014Assignee: Moses Lake Industries, Inc.Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
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Publication number: 20130344659Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.Type: ApplicationFiled: August 22, 2013Publication date: December 26, 2013Inventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
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Patent number: 8580679Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.Type: GrantFiled: August 20, 2007Date of Patent: November 12, 2013Assignee: Intel CorporationInventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
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Patent number: 8541876Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.Type: GrantFiled: September 30, 2005Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
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Patent number: 8319287Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.Type: GrantFiled: February 12, 2010Date of Patent: November 27, 2012Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
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Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
Patent number: 8278121Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.Type: GrantFiled: September 23, 2011Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett -
METHOD AND APPARATUS TO FABRICATE POLYMER ARRAYS ON PATTERNED WAFERS USING ELECTROCHEMICAL SYNTHESIS
Publication number: 20120225512Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.Type: ApplicationFiled: May 16, 2012Publication date: September 6, 2012Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett -
Publication number: 20120199491Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.Type: ApplicationFiled: April 20, 2012Publication date: August 9, 2012Applicant: MOSES LAKE INDUSTRIESInventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard