Patents by Inventor Valery M. Dubin

Valery M. Dubin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190198472
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 27, 2019
    Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
  • Patent number: 10249588
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 10035147
    Abstract: An embodiment of the invention relates to a wafer comprising a plurality of biochips and interconnects on the wafer, the biochip comprising a biochip pad, a synthesis electrode and a gel comprising a probe, wherein a plurality of the biochip pads of the plurality of the biochips are interconnected by the interconnects to carry out a chemical reaction on a plurality of the synthesis electrodes.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Publication number: 20170084564
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
  • Patent number: 9543261
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 9508675
    Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
  • Publication number: 20150231633
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Application
    Filed: December 31, 2014
    Publication date: August 20, 2015
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Patent number: 9085461
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 21, 2015
    Assignee: INTEL CORPORATION
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Publication number: 20150096894
    Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
  • Patent number: 8940143
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Patent number: 8911609
    Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Moses Lake Industries, Inc.
    Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
  • Publication number: 20130344659
    Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
    Type: Application
    Filed: August 22, 2013
    Publication date: December 26, 2013
    Inventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
  • Patent number: 8580679
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 8541876
    Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 24, 2013
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Chuan Hu, Gilroy J. Vandentop, Shriram Ramanathan, Rajashree Baskaran, Valery M. Dubin
  • Patent number: 8319287
    Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
  • Patent number: 8278121
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Publication number: 20120225512
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 6, 2012
    Inventors: Valery M. Dubin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
  • Publication number: 20120199491
    Abstract: Embodiments of the invention are directed to methods of electroplating copper onto at least one surface of a substrate in which more uniform electrical double layers are formed adjacent to the at least one surface being electroplated (i.e., the cathode) and an anode of an electrochemical cell, respectively. In one embodiment, the electroplated copper may be substantially-free of dendrites, exhibit a high-degree of (111) crystallographic texture, and/or be electroplated at a high-deposition rate (e.g., about 6 ?m per minute or more) by electroplating the copper under conditions in which a ratio of a cathode current density at the at least one surface to an anode current density at an anode is at least about 20. In another embodiment, a porous anodic film may be formed on a consumable copper anode using a long conditioning process that promotes forming a more uniform electrical double layer adjacent to the anode.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 9, 2012
    Applicant: MOSES LAKE INDUSTRIES
    Inventors: Valery M. Dubin, Xingling Xu, Yingxiang Tao, James D. Blanchard
  • Patent number: 8227335
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Publication number: 20120070930
    Abstract: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 22, 2012
    Inventors: Valery M. DuBin, Florian Gstrein, Gordon D. Holt, Brandon Barnett