Abstract: Disclosed are embodiments of a method of forming metal interconnects using a sacrificial layer to protect a seed layer prior to metal gap fill. The sacrificial layer can prevent oxidation of the seed layer and perhaps oxygen migration to an underlying barrier layer. Other embodiments are described and claimed.

Abstract: An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: A method comprising forming an interconnection opening through a dielectric material to a contact point; and electroplating a interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine. A method comprising forming an interconnection opening through a dielectric material to a contact point; lining the interconnection opening with a barrier layer and a seed layer; and electroplating an interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine.

Abstract: A method for forming a trench with a flared opening in a dielectric layer comprises providing a semiconductor substrate having a dielectric layer deposited thereon, depositing and patterning a photoresist layer atop the dielectric layer to form at least two photoresist structures, applying a plasma etch to define a flared trench profile in the photoresist structures, and applying a dry etch chemistry to etch a trench in the dielectric layer using the photoresist structures as a mask, wherein the flared trench profile is transferred from the photoresist structures to the dielectric layer. The dry etch chemistry may comprise an anisotropic plasma etch.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: A method of processing a substrate is described. A coupling agent and a metal ion solution are applied to the substrate. An activating solution is applied to activate metal ions of the metal ion solution to create a metal film out of the ions. Atoms of the metal film are used to catalyze a metal of a base metal solution to form a metal layer. The metal layer can be used as a seed layer for electroplating purposes.

Abstract: A device includes an integrated circuit and a deposited tin in electrical contact with a portion of the integrated circuit. The deposited tin is formed by electrodeposition from a bath. The deposited tin includes a residue characteristic of the bath. The bath includes a bath-soluble tin compound, a strong acid, and a sulfopropylated anionic surfactant. In another aspect, a composition includes between approximately 20 and 40 grams per liter of one of stannous methane sulfonate, stannous sulfate, and a mixture thereof, between approximately 100 and 200 grams per liter of one of methanesulfonic acid, sulfuric acid, and a mixture thereof, and between approximately 1 and 2 grams per liter of one or more polyethyleneglycol alkyl-3-sulfopropyl diethers. In another aspect, a method includes electroplating tin with a current density of greater than approximately 30 mA/cm2 and a plating efficiency of greater than approximately 95%.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a thin conformal copper layer on a surface by utilizing a formation temperature below about 125 degrees Celsius.

Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: The present invention relates to a cobalt electroless plating bath composition. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.

Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: Some embodiments of the present invention include fabricating carbon nanotube bundles with controlled length, diameter, and metallic contacts.