Abstract: Systems and methods are provided for controlling the pressure of a working fluid at an inlet of a main pressurization device of a heat engine system. The heat engine system may include a control system and a working fluid circuit including a waste heat exchanger, an expansion device, a recuperator, a main pressurization device, and a heat exchanger assembly. The heat exchanger assembly may include a plurality of gas-cooled heat exchangers configured to transfer thermal energy from the working fluid to a cooling medium, a plurality of fans configured to direct the cooling medium into contact with the gas-cooled heat exchangers, and a plurality of drivers, each driver configured to drive a respective fan. The control system may be communicatively coupled to the heat exchanger assembly and configured to modulate a rotational speed of at least one fan to regulate a pressure of the working fluid at the inlet.

Abstract: Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.

Abstract: In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.

Abstract: Systems, methods, and computer-readable media for provisioning multiple credentials of a multi-scheme card on an electronic device for selective use in a secure transaction are provided.

Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.

Abstract: A system and method for power saving in power saving stations connected to a Very High Throughput (VHT) access point is disclosed. The access point receives triggers from power saving stations. The power saving stations are one of VHT Transmission Opportunity (TXOP) power saving stations and non-VHT TXOP power saving stations. Successively, Quality of service (QoS) requirements of buffered data for the power saving stations connected to the VHT access point is determined. In a first case, the QoS requirements of buffered data corresponding to the non-VHT TXOP power saving stations exceed the QoS requirements of the VHT TXOP power saving stations. During the first case, the VHT TXOP power saving stations are sent into a sleep state and buffered data corresponding to the non-VHT TXOP power saving stations is transmitted.

Abstract: A method for handling namespace reservations in a Non Volatile Memory express (NVMe) controller includes a NVMe hardware module collecting a data access request from a host device, the NVMe hardware module determining a validity of the collected data access request, wherein the validity of the data access request is determined based a reservation specific to the host and data indicated in the data access request, and the NVMe hardware module notifying the NVMe firmware module of the determined validity of the collected data access request. The method further includes a NVMe firmware module accepting the data access request when the data request is notified by the NVMe hardware module as being valid, and the NVMe firmware module rejecting the data access request when the data request is notified by the NVMe hardware module as being invalid.

Abstract: A system and method for power saving in power saving stations connected to a Very High Throughput (VHT) access point is disclosed. The access point receives triggers from power saving stations. The power saving stations are one of VHT Transmission Opportunity (TXOP) power saving stations and non-VHT TXOP power saving stations. Successively, Quality of service (QoS) requirements of buffered data for the power saving stations connected to the VHT access point is determined. In a first case, the QoS requirements of buffered data corresponding to the non-VHT TXOP power saving stations exceed the QoS requirements of the VHT TXOP power saving stations. During the first case, the VHT TXOP power saving stations are sent into a sleep state and buffered data corresponding to the non-VHT TXOP power saving stations is transmitted.

Abstract: A striker mounting structure of a rear seat back for a vehicle is disclosed, which comprises a mounting bracket with assemble hole; a striker fixedly coupled to the mounting bracket with inserted into the assemble hole, and detachably coupled to a seat back of a rear seat; and a seat belt retractor mounting portion at which a seat belt retractor is mounted, and coupled to the mounting bracket, so that it is possible to reduce weight and cost.

Abstract: Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.

Abstract: A mechanism is provided for interactively indicating information associated with a patient on a hospital garment. A set of questions is identified utilizing a set of information received from a plurality of sources within a medical facility. The set of information is analyzed for a set of key elements. The set of key elements is utilized to identify one or more questions from a search question database. The one or more questions are submitted to a request processing pipeline implemented by a healthcare cognitive system. Responsive to receiving a response from the request processing pipeline, one or more communications are identified to be sent to one or more hospital garments associated with the patient and/or medical staff. The one or more communications are sent to the one or more hospital garments to cause the one or more hospital garments to change a visual cue.

Abstract: Systems and methods are provided for controlling the pressure of a working fluid at an inlet of a main pressurization device of a heat engine system. The heat engine system may include a control system and a working fluid circuit including a waste heat exchanger, an expansion device, a recuperator, a main pressurization device, and a heat exchanger assembly. The heat exchanger assembly may include a plurality of gas-cooled heat exchangers configured to transfer thermal energy from the working fluid to a cooling medium, a plurality of fans configured to direct the cooling medium into contact with the gas-cooled heat exchangers, and a plurality of drivers, each driver configured to drive a respective fan. The control system may be communicatively coupled to the heat exchanger assembly and configured to modulate a rotational speed of at least one fan to regulate a pressure of the working fluid at the inlet.

Abstract: An application lifecycle manager manages the lifecycles of different applications. The application lifecycle manager allows for development teams to control how their applications are updated by providing script which performs the lifecycle task. The tool includes an interface that receives a package which includes the script, configuration information, any dependency data needed to implement the lifecycle task. Hence, the development teams have control over how their applications are updated modified because the package is passed through the interface directly to the application. The tool includes the interface receive the package, and includes logic to open the package and apply the package contents to the application as part of the lifecycle.

Abstract: A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.

Abstract: Memory management in a multi-core solid state drive (SSD) includes distributing, by a memory access management system, multiple direct memory access (DMA) descriptors that describe a mechanism to access a local memory of each processor among multiple processors in the multi-core solid state drive. A direct memory access engine is configured with logical addresses corresponding to locations described by the direct memory access descriptors in the local memory of each processor. The logical addresses emulate a continuous memory.

Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.

Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

Abstract: Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust output phase using a phase adjustment signal. In certain embodiments, the phase adjustment signal can be received in a signal path from an output of a time-to-digital converter of the DPLL to an input to the digitally controlled oscillator of the DPLL. Some embodiments relate to adjusting the output phase of the DPLL to reduce a relative phase difference between the output phase of the DPLL and an output phase of another DPLL.