Abstract: A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.

Abstract: A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.

Abstract: A method, system, and product within a logically partitioned computer system including multiple, different partitions are disclosed for booting a partition using one of multiple, different firmware images. These multiple, different firmware images are stored in the computer system. One of the partitions is rebooted utilizing one of the firmware images without rebooting other ones of the partitions.

Abstract: A method, apparatus and program for booting a non-uniform-memory-access (NUMA) machine are provided. The invention comprises configuring a plurality of standalone, symmetrical multiprocessing (SMP) systems to operate within a NUMA system. A master processor is selected within each SMP; the other processors in the SMP are designated as NUMA slave processors. A NUMA master processor is then chosen from the SMP master processors; the other SMP master processors are designated as NUMA slave processors. A unique NUMA ID is assigned to each SMP that will be part of the NUMA system. The SMPs are then booted in NUMA mode in one-pass with memory coherency established right at the beginning of the execution of the system firmware.

Abstract: A method, system, and computer program product for enforcing logical partitioning of a shared device to which multiple partitions within a data processing system have access is provided. In one embodiment, a firmware portion of the data processing system receives a request from a requesting device, such as a processor assigned to one of a plurality of partitions within the data processing system, to access (i.e., read from or write to) a portion of the shared device, such as an NVRAM. The request includes a virtual address corresponding to the portion of the shared device for which access is desired. If the virtual address is within a range of addresses for which the requesting device is authorized to access, the firmware provides access to the requested portion of the shared device to the requesting device. If the virtual address is not within a range of addresses for which the requesting device is authorized to access, the firmware denies the request.

Abstract: A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system. The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system. The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions.

Abstract: A method for managing system firmware in a data processing system having a plurality of logical partitions is provided. Responsive to a request to update the system firmware from a first logical partition within the plurality of logical partitions in the data processing system, a determination is made whether the first logical partition within the plurality of logical partitions is present in the data processing system. Responsive to the determination that the first logical partition within the plurality of logical partitions is present in the data processing system, the system firmware is updated from the first logical partition in the data processing system. Then starting of additional partitions within the plurality of logical partitions in the data processing system is inhibited until the firmware update from the first logical partition is complete.

Abstract: A method, system, and product are described for configuring remote input/output (RIO) hubs within a data processing system. Each one of the RIO hubs is assigned to one of multiple slave processors which are included within the data processing system. Each one of the slave processors which has an assigned RIO hub then configures its assigned RIO hub. Each RIO hub has an associated data structure that is updated with current configuration information by the slave processor assigned to configure that RIO hub. When the slave processor has finished configuring its assigned RIO hub, the slave processor then sets a configuration flag to indicate the completion of the configuration of the RIO hub.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

Abstract: A method, system and program for architecturally identifying data processor implementations are provided. The invention comprises assigning a plurality of least significant bits in a processor's identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.

Abstract: A method and apparatus preserve the data structures established in the earliest stage of initial power load, rather than each system firmware component rediscovering the hardware components of the system. Thus, the data structure is available at later stages for other firmware components. In a logical partitioning machine, the open firmware partition manager can utilize the data structure to support the partition's open firmware device tree construction. The partition manager customizes the copies of these data structures residing in the partition's memory. For hardware devices in the system but not belonging to the partition, the device information is cleared and marked invalid. After the data structures are established and updated by the earliest firmware I/O configuration component, the addresses of these structures are provided to the open firmware component. The open firmware copies these data structures to its internally safe working area and uses the copies for its normal operation.

Abstract: A processor register is reserved by early firmware code to be employed for checkpoint logging or for storing diagnostic information at the time of failure before a checkpoint display device, usually contained within an I/O subsystem, is initialized. Early firmware codes are usually written in assembly language and the firmware of the present invention dedicates a processor register for logging checkpoint information. If a machine fails before any checkpoint, or point of failure, is displayed by a checkpoint display device, a dedicated processor register has logged any checkpoint or diagnostic information. The error information relating to the failure is obtained from the dedicated register through JTAG (Joint Task Action Group) scanning utilizing a processor debugging tool.

Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.

Abstract: A first copy of Open Firmware is loaded into system memory to supply a debug function and a second copy of the same firmware is then loaded to provide functional code which is to be debugged. The first copy of Open Firmware in system memory is designated as the resident debugging function. Kernel code, within the first copy, sets up an executing environment for the debugger, such as system exception handlers and debug console enablement. Normal Open Firmware configuration variables are retrieved from Non-Volatile Random Access Memory (“NVRAM”) by the first copy and transmitted to the loader. The second copy of Open Firmware is loaded into system memory to a location specified by the configuration variables. The second copy firmware image is designated as a normal Open Firmware operation in the system. The second copy initially takes over all system exception handlers except instruction breakpoint exception, program interrupt exception and trace exception.

Abstract: A system and method for determining which processor is to be the master processor in a symmetric multi-processor (SMP) environment. The determination is made by boot-level code, i.e. the software program which executes first in a processor after it is brought on-line. Each processor in the SMP system is brought on-line independently of the other processors in the system, and each processor in the system can uniquely identify itself. As a processor comes on-line, it checks to see if a master processor has already been designated. If not, the processor checks to see if another processor, with a higher priority identifier, has identified itself as a working processor. If so, the processor commits to being a slave processor. If not, the processor indicates that it is available to be the master processor. A further check is made to ensure that only one processor has indicated that it is available to become the master processor.

Abstract: A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Abstract: A method of saving the context of a plurality of registers in a computer processor, requires determining whether the processor registers have a first size or a second size, and saving the contents of the registers in a buffer using a first set of instructions if the processor registers have the first size (e.g., 64 bits), and using a second set of instructions if the processor registers have the second size (e.g., 32 bits). If the processor registers having the first size, the method may further include the steps of determining whether the processor is operating in a first mode (e.g., 64-bit mode) or a second mode (e.g., 32-bit mode), and then saving the contents of the registers in the buffer using the first set of instructions if the processor is operating in the first mode, but using the second set of instructions if the processor is operating in the second mode.

Abstract: An apparatus and method for booting a multiprocessor computer system including providing a first portion of boot code to multiple processors for execution, selecting a first processor, the selection based on which of the multiple processors first successfully executes the first portion of the boot code, providing a second portion of the boot code only to the first processor, and the first processor executing the second portion of the boot code to configure the multiprocessor system.

Abstract: One aspect of the invention relates to a method useful in a multiprocessor system for operating a processor. In one version of the invention, the method includes the steps of storing halt signature data in a register on the processor, the halt signature data being representative of whether the processor is in a halt state, storing start address data in memory which is accessible by the processor, executing an interruptible spin loop with the processor, and comparing the halt signature data with a predetermined halt signature to determine whether the processor is in a halt state when an interrupt is received and reading the start address data from memory to determine whether there is a request to start if the processor is in a halt state.