Abstract: In one example, a method comprises programming a memory cell capable of storing any of N values with 1 of the N values; applying a series of currents of increasing size to a bit line of the memory cell; comparing a voltage of the bit line to a reference voltage to generate a comparison output; and when the comparison output changes value, measuring a voltage of a control gate terminal of the memory cell and storing the voltage in a bias lookup table.

Abstract: A first example comprises programming a memory cell to store a value; applying a series of currents of increasing size to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias. A second example comprises programming a memory cell to store a value; applying a predetermined current to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W? values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)?(W?).

Abstract: Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network. In one embodiment, the gain of an output block can be configured by a configuration signal. In another embodiment, the resolution of an ADC in the output block can be configured by a configuration signal.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

Abstract: A method for partially publishing edits to a document is described. A first document including a first cell and a second cell is displayed on first user account on a first computing device and on a second user account. A second document including a linked version of the first cell and a linked version of the second cell is displayed. An edit of the first cell is received from the first user account and an edit of the second cell is received. In response to receiving an indication from the first user account that the edit of the first cell is to be published, the edit of the first cell is made to the linked version of the first cell, while the linked version of the second cell is unchanged so that the content of the linked version of the second cell no longer matches that of the second cell.

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

Abstract: A method and system for reforming CO2 rich natural gases is disclosed which comprises: a cold plasma unit configured to convert CO2 rich natural gases into a plasma state; and a gas reforming reactor configured to reform said CO2 rich gas mixture at said plasma state into a syngas. The catalytic reforming reactor is separate and different from the DBD cold plasma unit. Means for latent heat of condensation, endothermic/exothermic reactions, and convection currents is used to achieve energy efficiency.

Abstract: Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract: The composition is an herbal supplement comprised of hydrolyzed whole soybean, Bacillus amyloliquefaciens, lactic acid bacteria, the mushroom, Auricularia polytricha, and turmeric. The soybean feeds the bacterial components of the composition to increase their biomass. The Bacillus amyloliquefaciens produces protease and amylase enzymes which hydrolyze the proteins and carbohydrates in the soybean into smaller peptides and oligosaccharides. These smaller nutrients are more easily absorbed by the gastrointestinal tract. The lactic acid bacteria are probiotics which limit the growth of Bacillus amyloliquefaciens in the composition thus balancing the gastrointestinal microbiome. The mushroom, Auricularia polytricha enhances blood flow, removes toxins from the bowel, stabilizes the digestive system and enhances digestion. Turmeric is an antioxidant, anti-ulcer, anti-bacteria (including the suppression of Helicobacter pylori bacteria), anti-inflammatory.

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

Abstract: In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving a first voltage, multiplying the first voltage by a coefficient to generate a second voltage, applying the first voltage to a gate of one of a reference transistor and a selected memory cell, applying the second voltage to a gate of the other of a reference transistor and a selected memory cell, and using the reference transistor in a sense operation to determine a value stored in the selected memory cell.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

Abstract: A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

Abstract: Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplication array in an artificial neural network; and a plurality of reference arrays characterized by different I-V curves, wherein one or more of the plurality of reference arrays are used to generate input voltage the vector-by-matrix multiplication array during operation.

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential, a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address, and a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array.