Abstract: Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W? values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)?(W?).

Abstract: Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

Abstract: Examples of programming circuits and methods are disclosed. In one example, an adjustable programming circuit for generating a programming voltage is disclosed, the circuit comprising an operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving a reference voltage; a first switched capacitor network coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and a second switched capacitor network coupled between an input voltage and the second input terminal of the operational amplifier; wherein the output terminal of the operational amplifier outputs a programming voltage that varies in response to a capacitance of the first switched capacitor network and a capacitance of the second switched capacitor network.

Abstract: An implant delivery system including a fixation member delivery system including an elongate shaft, first and second rails, a plurality of fixation members with each fixation member slidably disposed on the first and second rails and an actuation assembly. The actuation assembly includes a first elongate member including a first plurality of engagement members disposed along the first elongate member with a distal end region of each engagement member in engagement with one of the fixation members, a second elongate member including a second plurality of engagement members disposed along the second elongate member with a distal end region of each engagement member in engagement with one of the fixation members. Additionally, cyclical actuation of the actuation assembly is configured to incrementally move the fixation members distally along the first and second rails to deploy each of the plurality of fixation members in sequence.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W? values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)?(W?). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W? values.

Abstract: Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in analog form when used in an analog neural memory system or in digital form when used in a digital neural memory system. Input circuitry and output circuitry are capable of supporting both forms of weight data.

Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

Abstract: The present invention relates to a water heat dissipating system used for a condenser coil of a water filter apparatus, the system comprising: said condenser coil of the water filter apparatus including a bent refrigerant pipeline part with a suitable shape for transferring heat from refrigerant conducted by the condenser coil to outside; a water heat dissipating container for containing water therein, the water heat dissipating container having a water heat dissipating container inlet and a water heat dissipating container outlet to circulate water contained in the water heat dissipating container. The bent refrigerant pipeline part is arranged inside the water heat dissipating container for transferring heat from refrigerant conducted inside the bent refrigerant pipeline part to water contained in the water heat dissipating container. The water heat dissipating container inlet is connected to at least a waste water outlet of a RO filter cartridge (Reverse Osmosis) of the water filter apparatus.

Abstract: The present invention relates to a water filter comprising: a water filter cartridge including a water filter cartridge body, a water filter cartridge outlet cap having a water filter cartridge outlet, and a water filter cartridge sealing cap. The water filter cartridge body in a hollow cylinder form with a central hollow space, one end of the water filter cartridge body is coupled with the water filter cartridge outlet cap so that communicating with the water filter cartridge outlet, and the another end of the water filter cartridge body is coupled with the water filter cartridge sealing cap. The water filter cartridge outlet in a hollow cylinder form protruding from one surface of the water filter cartridge outlet cap.

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

Abstract: Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In some embodiments, a common mode circuit is used with differential cells, W+ and W?, that together store a weight, W. The common mode circuit can utilize current sources, variable resistors, or transistors as part of the structure for introducing a common mode voltage bias.

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.