Patents by Inventor Van Tran

Van Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Architectures for storing and retrieving system data in a non-volatile memory system
    Patent number: 11538532
    Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 27, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20220405564
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 22, 2022
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network
    Patent number: 11532354
    Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20220398444
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 15, 2022
    Inventors: Hieu Van TRAN, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
  • Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network
    Publication number: 20220391682
    Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving a first voltage, multiplying the first voltage by a coefficient to generate a second voltage, applying the first voltage to a gate of one of a reference transistor and a selected memory cell, applying the second voltage to a gate of the other of a reference transistor and a selected memory cell, and using the reference transistor in a sense operation to determine a value stored in the selected memory cell.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 8, 2022
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array
    Patent number: 11521682
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: December 6, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • Programming analog neural memory cells in deep learning artificial neural network
    Patent number: 11521683
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 6, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • TENSIONABLE AND LOCKABLE SOFT SUTURE ANCHORS AND ANCHOR ARRAYS FOR ANATOMICAL ATTACHMENT OF SOFT TISSUE TO BONE
    Publication number: 20220378409
    Abstract: Soft suture anchors are disclosed that can be formed into a pre-strung array with a common working suture. Each anchor includes the common working suture and a soft anchor member that is expandable when implanted. This allows first locking an individual anchor into a bone hole followed by tensioning the suture and independently locking the suture at the anchor. A first anchor is implanted through the tendon and the suture is locked. A second anchor is implanted a selected close distance from the first anchor, the working suture is tensioned between the first and second anchors, and the working suture is locked at the second anchor to create a single suture tensioned and locked stitch between the first and second anchor. This process is repeated for each anchor in the array.
    Type: Application
    Filed: February 24, 2022
    Publication date: December 1, 2022
    Inventors: Zak Zenz-Olson, Nathaniel Van Tran, Thomas A. Westling, Howard W. Harris, David M. Crompton, Patrick M. Connor
  • COMPENSATION FOR REFERENCE TRANSISTORS AND MEMORY CELLS IN ANALOG NEURO MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20220383087
    Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20220383086
    Abstract: Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a method for performing a read or verify operation in a vector-by-matrix multiplication system comprising an input function circuit, a memory array, and an output circuit block is disclosed, the method comprising receiving, by the input function circuit, digital bit input values; converting the digital input values into an input signal; applying the input signal to control gate terminals of selected cells in the memory array; and generating, by the output circuit block, an output value in response to currents received from the memory array.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 1, 2022
    Inventors: HIEU VAN TRAN, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • NON-VOLATILE MEMORY CELL ARRAY FORMED IN A P-WELL IN A DEEP N-WELL IN A P-SUBSTRATE
    Publication number: 20220375952
    Abstract: Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which reduces the peak positive voltage required to be applied to the cells to cause the cells to erase.
    Type: Application
    Filed: August 30, 2021
    Publication date: November 24, 2022
    Inventors: Hieu Van Tran, Nhan Do
  • PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
    Publication number: 20220374699
    Abstract: Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • OUTPUT CIRCUIT FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20220374161
    Abstract: Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W? bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.
    Type: Application
    Filed: August 31, 2021
    Publication date: November 24, 2022
    Inventors: Hieu Van Tran, Thuan Vu, Mark Reiten
  • SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20220374696
    Abstract: Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.
    Type: Application
    Filed: August 30, 2021
    Publication date: November 24, 2022
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
  • Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
    Patent number: 11507816
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network
    Patent number: 11507642
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
  • System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
    Patent number: 11500442
    Abstract: Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network. Numerous embodiments are disclosed for converting the neuron current-based time pulses into analog current or voltage values if an analog input is needed for the VMM array.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 15, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • METHOD FOR PARTIALLY PUBLISHING EDITS TO A DOCUMENT
    Publication number: 20220358284
    Abstract: A method for partially publishing edits to a document is described. A first document including a first cell and a second cell is displayed on first user account on a first computing device and on a second user account. A second document including a linked version of the first cell and a linked version of the second cell is displayed. An edit of the first cell is received from the first user account and an edit of the second cell is received. In response to receiving an indication from the first user account that the edit of the first cell is to be published, the edit of the first cell is made to the linked version of the first cell, while the linked version of the second cell is unchanged so that the content of the linked version of the second cell no longer matches that of the second cell.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 10, 2022
    Inventors: Hannah Joy Deering, Thieu Van Tran Pham, Travis Smith, Edward Joseph Cupps, Aaron David Hall, Matthew Peter Hinrichsen, Ryan A. King, Joshua John Przybyszewski, Madelyn Renee Stephens
  • Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
    Patent number: 11482530
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 25, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM
    Publication number: 20220336010
    Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Hieu Van Tran, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO