Abstract: A traffic management processor for managing a number of traffic flows each including one or more packets includes a content address memory (CAM) device having a plurality of rows, each row storing a flow identification (ID) for a corresponding packet, the flow ID indicating to which traffic flow the packet belongs, a departure time table for storing departure times for the packets, and compare logic for comparing the departure times with each other to determine which departure time is the earliest.

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of the CAM cells, each pair of data lines including at least one data line that is formed by conductive segments disposed in two different conductivity layers of the CAM device.

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first data line pairs, each second data line pair having a first and second constituent data lines that cross one another at a point along their lengths.

Abstract: A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.

Abstract: A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives the address value from the encoding circuit and enables a data word to be output from a CAM array storage location indicated by the address value. The error checking circuit receives the data word output from the storage location and determines whether the data word contains an error.

Abstract: A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit, and a reset circuit configured to reset the rollover bits in a predetermined time.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: A content addressable memory (CAM) device having concurrent compare and error checking capability. The content addressable memory (CAM) device includes circuitry to compare a comparand with a plurality of data words stored within the CAM device in a compare operation, and circuitry to determine, concurrently with the compare operation, whether one of the data words has an error.

Abstract: A method and apparatus for input data selection for content addressable memory. In one embodiment, the apparatus includes an array of CAM cells, a select circuit adapted to generate a plurality of select signals each indicative of a segment of input data provided to the CAM apparatus, and switch circuitry including a plurality of programmable switch circuits each programmable to output a respective bit of the input data as a comparand bit for the array of CAM cells in response to one of the select signals.

Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) Address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells, a group global mask circuit, and a mask valid bit indicating whether the group global mask circuit stores a valid group global mask.

Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.

Abstract: A method of operation within a content addressable memory (CAM) device. An input data word having a plurality of data bits and a plurality of mask bits is received in the CAM device. An encoded data word is generated based, at least in part, on states of the mask bits within the input data word. A write data word is selected from a group of data words that includes at least the input data word and the encoded data word. The write data word is stored within a row of CAM cells within the CAM device.

Abstract: A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array.

Abstract: A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a priority number that indicates the priority of the policy statement relative to other policy statements. The priority numbers are separately stored in a priority index table. The priority index table includes priority logic that determines the most significant priority number from among the policy statements that match an incoming packet during a classification of filter operation. The priority logic also identifies the location in the priority index table of the most significant priority number. The identified location in the priority index table can be used to access associated route information or other information stored in a route memory array.

Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.

Abstract: The apparatus for the preparation of an end-aligned fiber sample comprises an array of fiber combs, a first drive unit, a fiber collection device connected to the first drive unit, a suction device, a detection device and a control unit to control each of the foregoing components. The method for preparing an end-aligned fiber sample uses the control unit to operate each of the foregoing components to prepare an end-aligned fiber sample. The apparatus can be combined with testing units for testing the end-aligned fiber samples. One of the testing units can test for short fiber content. The testing for short fiber content also can employ the detection device of the apparatus.