Abstract: A content addressable memory (CAM) cell. The CAM cell includes a first and second memory cells and a diffusion region. First and second transistors are formed adjacent one another in the diffusion region and coupled to the first memory cell, and third and fourth transistors are formed adjacent one another in the diffusion region and coupled to the second memory cell.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: A content addressable memory (CAM) architecture. In one embodiment, the CAM architecture includes a CAM array including a plurality of rows of CAM cells to compare, in a first compare operation, comparand data with data stored in the rows and output match results on a plurality of match signal lines; a timed storage circuit having data inputs coupled to the match signal lines and an enable input; and a dynamic timing generator circuit including a first compare circuit to perform a second compare operation to generate an enable signal coupled to the enable input to enable the timed storage circuit to capture the match results.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, and circuitry to shift data corresponding to the defective column and data corresponding to all subsequent columns to corresponding adjacent non-defective columns.

Abstract: A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.

Abstract: A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in at least one of the row segments in response to first configuration information, and determines when second comparand data matches data stored in at least one group of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

Abstract: A method and apparatus for determining a match address in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information.

Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A content addressable memory (CAM) that includes a CAM array and a write circuit. The write circuit is coupled the CAM array and has a coding circuit to convert a first value into a second value, and a select circuit to select either the first value or the second value to be stored in the CAM array.

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Abstract: A CAM system includes two or more CAM devices having the same device identification number (DID). One or more priority address bits indicating priority between the CAM devices may be assigned to each CAM device. Each CAM device may receive a mode signal indicating whether the CAM device operates independently or in cooperation with other cascaded CAM devices. During compare operations, each CAM device generates a highest priority match (HPM) index. A selected number of the priority address bits are inserted between the DID and the HPM index to form a device index for the system. During read and write operations, a first portion of an input address is used to select a row of CAM cells in each CAM device. A second portion of the input address is compared to a selected number of the priority address bits to enable an array in one of the CAM devices.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, a steering circuit for steering data corresponding to the defective column to the spare column, and a global mask circuit for masking the defective column during a compare operation.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Abstract: A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.