Abstract: A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder.

Abstract: A selective look-ahead pre-charging technique is used in a CAM having a plurality of row segments that allows pre-charging operations in a row segment to be overlapped with compare operations in one or more preceding row segments. In one embodiment, each row includes four row segments each having a plurality of CAM cells coupled to a corresponding match line segment. The first and second match line segments are pre-charged to enable detection of match conditions therein. The third match line segment is selectively pre-charged in response to match conditions in the first row segment, and the fourth match line segment is selectively pre-charged in response to match conditions in the second row segment. If there are match conditions in all row segments, a match condition is indicated for the row. If there is a mismatch condition in any row segment, a mismatch condition is indicated.

Abstract: A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract: An almost full flag is asserted when all but one of the rows of a CAM array contain valid data, as indicated by corresponding valid bits. In one embodiment, the almost full flag is generating using match logic and multiple match logic, where the match logic asserts a first signal when at least one of the CAM rows contains invalid data, and the multiple match logic asserts a second signal when more than one CAM row contains invalid data. The almost full flag is asserted when the first asserting is asserted indicating there is at least one available row and the second signal is de-asserted indicating there is no more than one available row. Thus, when asserted, the almost full flag indicates that there is only one available CAM row. Subsequent instructions are monitored to detect an instruction which calls for writing valid data to the one available CAM row. The full flag is asserted when such an instruction is detected while the almost full flag is asserted.

Abstract: A content address memory (CAM) device that implements a read next highest priority or “RNHPM” instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority matching address. The CAM device may output the highest priority matching address in the same system or a later clock cycle in which the compare instruction was provided. The CAM device may also output data stored in one or more of the CAM cells located at the highest priority matching location and/or status information including the match flags, a full flag, validity bits (e.g., skip and empty bits), and other status information. An RNHPM instruction may then be provided to the CAM device in the next clock cycle or a later clock cycle and cause the next highest priority matching address to be output by the CAM device.

Abstract: A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to generate a system match flag are each logarithmically related to the number of cascaded devices. In one embodiment, an m-level hierarchy of groups are defined for up to n memory devices, where m=log2n and m is an integer greater than 2. The first hierarchy is defined as including n/2 groups of 2 memory devices, the second hierarchy is defined as including n/4 groups of 4 memory devices, and so on, until a final hierarchy of one group is defined. Each group in a given hierarchical level includes a pair of groups from the preceding hierarchical level.

Abstract: A method and apparatus for performing row redundancy in a CAM device. For one embodiment, the CAM device includes a main CAM array having a plurality of rows of CAM cells, main match line control circuitry coupled to the main CAM array, a spare row of CAM cells, and a spare match line control circuit coupled to the spare row of CAM cells. The main CAM array includes a plurality of main match lines each coupled to one of the plurality of rows of CAM cells, and a plurality of main word lines each coupled to one of the plurality of rows of CAM cells. For one embodiment, the main match line control circuitry comprises a plurality of latch circuits each having a data input coupled to one of the main word lines, an output coupled to one of the main match lines, and a clock input responsive to a reset signal and a repair signal. The repair signal indicates whether one of the plurality or rows in the first main CAM array is to be replaced by the spare row of CAM cells.

Abstract: A content address memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A CAM system for storing a data word chain having a sequence of one or more data words stored in one or more rows of CAM cells. For one embodiment, the CAM system includes rows of CAM cells each for storing a data word in a data word chain, match lines, and width expansion logic circuits each having a plurality of control inputs for receiving a plurality of control signals. The width expansion logic circuits are interconnected and determine when and how match results are communicated to a priority encoder and to each other. The control signals are for determining the operation of the width expansion logic circuits and for indicating when a first data word, a continuing data word, and a last data word of the data word chain are provided for comparison with the rows of CAM cells. The continuing data word is a data word between the first and last data word in the data word chain.

Abstract: A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder. During subsequent read or write operations, an input address is compared with the programmed addresses stored in the spare address decoders.

Abstract: Rows of a CAM array are partitioned into a plurality of row segments, with each row segment having a corresponding match line segment. A first match line segment is pre-charged to enable detection of match conditions in the associated first row segment. Subsequent match line segments are then selectively charged in response to the match conditions in the preceding row segments. In one embodiment, rows of a CAM array are partitioned into first and second row segments. A first match line segment is pre-charged to enable detection of match conditions within the associated first row segment. If there is a match condition in the first row segment, a second match line segment is charged to enable detection of match conditions in the associated second row segment. If there is a match condition in the second row segment, a match condition is indicated for the row. If there is not a match condition in the second row segment, a mismatch condition is indicated for the row.

Abstract: A method and apparatus for implementing a LEARN instruction in a depth cascaded content address memory (CAM) system. Each CAM device in the CAM system may include a CAM array, an input coupled to the CAM array and configured to receive comparand data to be compared with data stored in the CAM array, circuitry coupled to the CAM array and configured to write the comparand data into the CAM array if the comparand data does not match the data stored in the CAM array, and cascade logic coupled to the circuitry and configured to receive a plurality of match flag input signals, the cascade logic configured to disable the circuitry from writing the comparand data into the CAM array if the comparand data matches the data stored in the CAM array. Each CAM device may have a match flag input pin and output pin coupled to a match flag output pin and input pin, respectively, of the previous device and next device in the depth cascaded CAM system.

Abstract: A ternary content addressable memory is employed to perform a longest prefix match search. Each CAM cell within the ternary CAM has an associated mask cell so that the CAM cells may be individually masked so as to effectively store either a logic 0, a logic 1, or a don't care for compare operations. For example, Classless Inter-Domain Routing (CIDR) addresses are pre-sorted and loaded into the ternary CAM such that the CAM entry having the longest prefix is located at the lowest numerical address or index of the ternary CAM, and the CAM entry with the shortest prefix is located at the highest numerical address or index. The prefix portions of the CIDR addresses are used to set the mask cells associated with each CAM entry such that during compare operations, only the unmasked prefix portion of each CAM entry is compared to an incoming destination address stored as the CAM search key.

Abstract: A method and apparatus for performing row redundancy in a CAM device. For one embodiment, the CAM device includes a main CAM array having a plurality of rows of CAM cells, main match line control circuitry coupled to the main CAM array, a spare row of CAM cells, and a spare match line control circuit coupled to the spare row of CAM cells. The main CAM array includes a plurality of main match lines each coupled to one of the plurality of rows of CAM cells, and a plurality of main word lines each coupled to one of the plurality of rows of CAM cells. For one embodiment, the main match line control circuitry comprises a plurality of latch circuits each having a data input coupled to one of the main word lines, an output coupled to one of the main match lines, and a clock input responsive to a reset signal and a repair signal. The repair signal indicates whether one of the plurality or rows in the first main CAM array is to be replaced by the spare row of CAM cells.

Abstract: A content address memory (CAM) device that implements a “LEARN” instruction. In response to the LEARN instruction, the CAM device compares comparand data with data stored in a CAM array of the CAM device. If a match is not found, the comparand data is written into the CAM array. For one example, the comparand data is written to the next free address of the CAM array. The learn instruction may further cause the CAM device to output the next free address after the comparand data has been written into the CAM array. For one embodiment, the learn instruction may be implemented in a single clock cycle.

Abstract: A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: Match line control circuits are used to selectively charge corresponding match lines in response to the valid bits. If the valid bit is asserted, thereby indicating the valid data is stored in the CAM row, the match line control circuit pre-charges the match line to enable the match line to be responsive to compare operation between a comparand word and data stored in the row. If the valid bit is de-asserted, thereby indicating that any data stored in the row is invalid, the match line control circuit disables the match line by forcing a mismatch condition between the comparand word and data stored in the row. In one embodiment, the match line control circuit includes a pull-up transistor coupled between the match line and a supply voltage and having a gate responsive to the valid bit. In other embodiments, the match line control circuit further includes a pull-down transistor coupled between the match line and a supply voltage and having a gate responsive to a complement of the valid bit.

Abstract: A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.

Abstract: A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal).