Abstract: A method and apparatus for simultaneously performing a plurality compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of CAM cells, a first comparand register for storing first comparand data, and a second comparand register for storing second comparand data. Each CAM cell receives the first comparand data over a first set of compare lines, and receives the second comparand data over a second set of compare lines. Each CAM cell has a memory cell and multiple compare circuits that can individually and simultaneously compare the first and second comparand data with data stored in the memory cell. The result of each comparison is reflected on a corresponding match line. The match lines are then selectively coupled to a priority encoder to determine a match address corresponding to each compare operation. For one embodiment, the CAM cells may be ternary CAM cells each having a mask cell.

Abstract: The device for the preparation of fibrous material to be tested comprises means for fastening said fibrous material, means for partitioning the fibrous material, and means for clamping and separating the fibrous material. The means for fastening, the means for partitioning and the means for clamping operate in essentially parallel surface planes. Since the device essentially operates by performing linear translations in surface planes, it is suited to automation, simple, maintenance-friendly and inexpensive.

Abstract: A priority encoder for generating a priority-encoded address which identifies the highest priority request line. According to one priority scheme, the active request line having the lowest address has the highest priority. The priority encoder is capable of generating the priority-encoded address by determining information corresponding to the most significant bits of the priority-encoded address and using this information in the computation of less significant bits of the priority-encoded address. Using purely combinatorial logic, including switch elements, the priority encoder is capable of computing lower order bits using feedback signals resulting from the computation of higher order bits, allowing successive computation of priority-encoded address bits, without necessitating the use of clocks or delay elements.

Abstract: A circuit and a method for detecting the presence of multiple active match lines in a content addressable memory is disclosed. The circuit includes at least one bus group for expressing a unary-encoded address portion of an active match line and, for each match line, an encoding circuit capable of activating a single member of each bus group according to the address of that match line when that match line is active. The multiple match detection circuit advantageously uses the property that each match line has a unique address, and therefore if there is more than one active match line, at least one bus group will have at least two active members. The multiple match detection circuit further comprises, for each bus group, an bus group detection-OR circuit for computing the logical bus group detection-OR of the members of that bus group.

Abstract: A no clean thermally dissipated soldering flux is shown which includes camphor as a flux base, an organic activator and an organic diluent. The camphor provides a tacky yet fluid medium which is thermally dissipated during the flux operation and leaves no undesirable residue which would require a postcleaning step.