Abstract: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A method for making a semiconductor device (10) includes providing an interconnect layer (14) over an underlying layer (12), forming a first insulating layer (16) over the interconnect layer, and forming an opening (18) through the insulating layer to the interconnect layer. A first conductive layer (24) is formed over the interconnect layer and in the opening. This is performed by plating so it is selective. A second conductive layer (28) in the opening is formed by displacement by immersion. This is performed after the first conductive layer has been formed. The result is the second conductive layer is formed by a selective deposition and is effective for providing it with bridging material. A layer of bridgeable material (34) is formed over the second conductive layer and in the opening. A third conductive layer (42) is formed over the bridgeable material. The semiconductor device may be useable as a conductive bridge memory device.

Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.

Abstract: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: A method for cleaning a metal plating tank is provided herein. In accordance with the method, the tank is exposed to a first acid (103), after which the tank is exposed to a second acid in the presence of a first oxidizing agent (107).

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.

Abstract: A method for cleaning a metal plating tank is provided herein. In accordance with the method, the tank is exposed to a first acid (103), after which the tank is exposed to a second acid in the presence of a first oxidizing agent (107).

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34) is formed at a top surface and a sidewall of the current electrode regions followed by an anisotropic etch of the conductive layer (32) used to form the thin silicide layer. The anisotropic etch of the conductive layer results in conductive spacers (36) adjacent sidewalls of the current electrode regions where these conductive spacers may allow for reduced contact resistance thus improving device performance. The conductive spacers may be formed adjacent current electrode regions of a MOSFET device, FINFET device, bipolar device, or Shotky-Barrier device.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.