Patents by Inventor Varughese Mathew

Varughese Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070049008
    Abstract: A method for making a semiconductor device includes forming a patterned dielectric overlying active circuitry, the patterned dielectric having a plurality of cavities. A diffusion barrier is formed over the patterned dielectric. A conductive layer is formed over the diffusion barrier in the plurality of cavities. The conductive layer is etched back to be below a top surface of the dielectric, forming recessed areas over the conductive layers in the plurality of cavities. The recessed areas are then filled with a capping film. The capping film and the diffusion barrier are removed to provide a relatively smooth planarized surface. Providing a relatively smooth planarized surface reduces leakage currents between conductors.
    Type: Application
    Filed: August 26, 2005
    Publication date: March 1, 2007
    Inventors: Gerald Martin, Sam Garcia, Varughese Mathew
  • Patent number: 7176133
    Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: February 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Steven M. Hues, Michael L. Lovejoy, Varughese Mathew
  • Publication number: 20060270234
    Abstract: A method for making a semiconductor device includes cleaning a semiconductor wafer after a chemical mechanical polishing (CMP) process to remove or reduce particles of copper, a corrosion inhibitor such as triazole, and a copper oxide layer on the copper layer. In order to prepare for plating the copper layer with a layer that functions as a barrier to copper migration or diffusion, the surface of the copper layer and the dielectric layer are treated with an oxidant, a surfactant, and copper-chelating agent. The copper-chelating is preferably a mild acid such as an organic acid. The oxidant is particularly useful in removing the corrosion inhibitor. The barrier layer, preferably conductive, is then plated on the surface of the copper layer. Subsequent interlayer dielectric layers and copper layers follow that can use the same process.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Inventors: Varughese Mathew, Edward Acosta, Sam Garcia, Lynne Michaelson
  • Publication number: 20060202339
    Abstract: A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Lynne Michaelson, Edward Acosta, Ritwik Chatterjee, Stanley Filipiak, Sam Garcia, Varughese Mathew
  • Publication number: 20060110911
    Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.
    Type: Application
    Filed: November 22, 2004
    Publication date: May 25, 2006
    Inventors: Steven Hues, Michael Lovejoy, Varughese Mathew
  • Publication number: 20060057792
    Abstract: A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34) is formed at a top surface and a sidewall of the current electrode regions followed by an anisotropic etch of the conductive layer (32) used to form the thin silicide layer. The anisotropic etch of the conductive layer results in conductive spacers (36) adjacent sidewalls of the current electrode regions where these conductive spacers may allow for reduced contact resistance thus improving device performance. The conductive spacers may be formed adjacent current electrode regions of a MOSFET device, FINFET device, bipolar device, or Shotky-Barrier device.
    Type: Application
    Filed: September 10, 2004
    Publication date: March 16, 2006
    Inventors: Varughese Mathew, Leo Mathew
  • Patent number: 6924232
    Abstract: An electroless plating process for forming a barrier film such as a cobalt tungsten boron film on copper interconnects lines of semiconductor wafers uses a plating bath of morpholine borane which provides higher thermal stability and range, allowing for greater compatibility with low k dielectric materials. Mixed chelating agents with different stability constants with a metal source are used to complex base metal such as copper which dissolves into solution, if any. A fluorosurfactant is used as a wetting agent and stabilizer.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 2, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Varughese Mathew, Sam S. Garcia, Christopher M. Prindle
  • Publication number: 20050048773
    Abstract: An electroless plating process for forming a barrier film such as a cobalt tungsten boron film on copper interconnects lines of semiconductor wafers uses a plating bath of morpholine borane which provides higher thermal stability and range, allowing for greater compatibility with low k dielectric materials. Mixed chelating agents with different stability constants with a metal source are used to complex base metal such as copper which dissolves into solution, if any. A fluorosurfactant is used as a wetting agent and stabilizer.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 3, 2005
    Inventors: Varughese Mathew, Sam Garcia, Christopher Prindle
  • Patent number: 6803323
    Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: October 12, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshmi Narayan Ramanathan, Douglas G. Mitchell, Varughese Mathew
  • Publication number: 20030224613
    Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Inventors: Lakshmi Narayan Ramanathan, Douglas G. Mitchell, Varughese Mathew