Patents by Inventor Venkatesan Murali
Venkatesan Murali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8518724Abstract: A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal.Type: GrantFiled: April 18, 2012Date of Patent: August 27, 2013Assignee: GTAT CorporationInventors: Christopher J. Petti, Mohamed M. Hilali, Theodore Smick, Venkatesan Murali, Kathy J. Jackson, Zhiyong Li, Gopalakrishna Prabhu
-
Publication number: 20130203251Abstract: An interposer is fabricated from a lamina. A donor body is provided, ions are implanted into a first surface of the donor body to define a cleave plane, a temporary carrier is separably contacted to the donor body, and the lamina is cleaved from the donor body. The lamina has front surface and a back surface, with a thickness from the front surface to the back surface. A via hole is formed in the lamina, where the via hole extends through the thickness of the lamina. The temporary carrier is removed from the lamina, and the lamina may be fabricated into an interposer for three-dimensional integrated circuit packages.Type: ApplicationFiled: June 7, 2012Publication date: August 8, 2013Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Venkatesan Murali, Arvind Chari, Gopal Prabhu
-
Publication number: 20130200497Abstract: The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 500 and 1050° C.Type: ApplicationFiled: July 26, 2012Publication date: August 8, 2013Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Venkatesan Murali, Thomas Edward Dinan, JR., Steve Bababyan, Gopal Prabhu, Christopher J. Petti
-
Publication number: 20130203205Abstract: A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.Type: ApplicationFiled: March 21, 2012Publication date: August 8, 2013Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Venkatesan Murali, Arvind Chari, Gopal Prabhu, Christopher J. Petti
-
Publication number: 20130200496Abstract: The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 100 and 600 ° C.Type: ApplicationFiled: July 26, 2012Publication date: August 8, 2013Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Venkatesan Murali, Thomas Edward Dinan, JR., Steve Bababyan, Gopal Prabhu
-
Publication number: 20130199611Abstract: The invention provides for a semiconductor wafer with a metal support element suitable for the formation of a flexible or sag tolerant photovoltaic cell. A method for forming a photovoltaic cell may comprise providing a semiconductor wafer have a thickness greater than 150 ?m, the wafer having a first surface and a second surface opposite the first and etching the semiconductor wafer a first time so that the first etching reduces the thickness of the semiconductor wafer to less than 150 ?m. After the wafer has been etched a first time, a metal support element may be constructed on or over the first surface; and a photovoltaic cell may be fabricated, wherein the semiconductor wafer comprises the base of the photovoltaic cell.Type: ApplicationFiled: February 5, 2012Publication date: August 8, 2013Applicant: Twin Creeks Technologies, Inc.Inventors: Venkatesan Murali, Gopal Prabhu, Thomas Edward Dinan, JR., Orion Leland
-
Publication number: 20120258561Abstract: In embodiments of the present invention an undoped amorphous, nanocrystalline or microcrystalline semiconductor layer and a heavily doped amorphous, nanocrystalline, or microcrystalline semiconductor layer are formed on a monocrystalline silicon lamina. The lamina is the base region of a photovoltaic cell, while the amorphous, nanocrystalline or monocrystalline layers serve to passivate the surface of the lamina, reducing recombination at this surface. In embodiments, the heavily doped layer additionally serves as either the emitter of the cell or to provide electrical contact to the base layer. The undoped and heavily doped layers are deposited at low temperature, for example about 150 degrees C. or less with hydrogen dilution. This low temperature allows use of low-temperature materials and methods, while increased hydrogen dilution improves film quality and/or conductivity.Type: ApplicationFiled: April 11, 2011Publication date: October 11, 2012Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Jian Li, Venkatesan Murali, Yonghua Liu, Dong Xu
-
Patent number: 8257995Abstract: A cleave plane is defined in a semiconductor donor body by implanting ions into the wafer. A lamina is cleaved from the donor body, and a photovoltaic cell is formed which comprises the lamina. The implant may cause some damage to the crystal structure of the lamina. This damage can be repaired by annealing the lamina using microwave energy. If the lamina is bonded to a receiver element, the receiver element may be either transparent to microwaves, or may reflect microwaves, while the semiconductor material absorbs the microwaves. In this way the lamina can be annealed at high temperature while the receiver element remains cooler.Type: GrantFiled: December 11, 2009Date of Patent: September 4, 2012Assignee: Twin Creeks Technologies, Inc.Inventors: Mohamed M Hilali, Venkatesan Murali, Gopal Prabhu, Zhiyong Li
-
Publication number: 20120220068Abstract: A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal.Type: ApplicationFiled: April 18, 2012Publication date: August 30, 2012Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Christopher J. Petti, Mohamed M. Hilali, Theodore Smick, Venkatesan Murali, Kathy J. Jackson, Zhiyong Li, Gopalakrishna Prabhu
-
Patent number: 8173452Abstract: A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device.Type: GrantFiled: December 29, 2010Date of Patent: May 8, 2012Assignee: Twin Creeks Technologies, Inc.Inventors: Christopher J. Petti, Mohamed M. Hilali, Theodore Smick, Venkatesan Murali, Kathy J. Jackson, Zhiyong Li, Gopalakrishna Prabhu
-
Patent number: 8115304Abstract: A method of implementing a discrete component in an integrated circuit package is described. The method includes steps of coupling the discrete component to a surface of a substrate of the integrated circuit package, coupling an integrated circuit die to the surface of the substrate, applying a first epoxy material, and applying a second epoxy material to the discrete component, where the first epoxy material is different from the second epoxy material.Type: GrantFiled: February 6, 2008Date of Patent: February 14, 2012Assignee: Xilinx, Inc.Inventors: Mukul Joshi, Venkatesan Murali
-
Patent number: 8101451Abstract: A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device.Type: GrantFiled: December 29, 2010Date of Patent: January 24, 2012Assignee: Twin Creeks Technologies, Inc.Inventors: Venkatesan Murali, Christopher J Petti, Theodore Smick, Mohamed M Hilali, Kathy J Jackson, Zhiyong Li, Gopalakrishna Prabhu
-
Publication number: 20110215465Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.Type: ApplicationFiled: March 3, 2010Publication date: September 8, 2011Applicant: XILINX, INC.Inventors: Arifur Rahman, Venkatesan Murali
-
Patent number: 7141448Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.Type: GrantFiled: June 5, 2001Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: Suresh Ramalingam, Venkatesan Murali, Duane Cook
-
Patent number: 7095937Abstract: A multi-level waveguide to transmit light through a series of substrates. The multi-level waveguide is made up of stacked substrates, each containing a two dimensional array of transparent material filled vias. Transparent materials such as optical fiber, cladding, and gas may be used to provide a pathway for light. Optionally, a conductive layer may be deposited on a substrate in the multi-level waveguide. The conductive layer can then interact with the multi-level waveguide through light detecting devices such as photodetectors.Type: GrantFiled: June 17, 2003Date of Patent: August 22, 2006Assignee: Intel CorporationInventor: Venkatesan Murali
-
Patent number: 7066657Abstract: An apparatus including a base having a first opening of a dimension suitable to pass a light emission therethrough, a first side wall coupled to the base and having a second opening of a dimension suitable to pass a light emission therethrough, a second side wall coupled to the base and having a reflective component thereon, and the base, the first side wall, and the second side wall define an interior chamber with the reflective component disposed in the interior chamber; and a fiber connector extending from an exterior of the first side wall adjacent the second opening. A method including powering a laser disposed in a substrate coupling a fiber optic cable to an optical subassembly; and aligning the optical assembly over the transceiver board to capture the emitted light from the laser in the fiber optic cable.Type: GrantFiled: December 28, 2000Date of Patent: June 27, 2006Assignee: Intel CorporationInventors: Venkatesan Murali, Douglas E. Crafts, Suresh Ramalingam, Brett M. Zaborsky, Siegfried B. Fleischer
-
Patent number: 7000434Abstract: A waveguide having an angled surface is created by depositing an optical core material onto a substrate having two levels. In one embodiment, a high density plasma deposition may be used to deposit the optical core material.Type: GrantFiled: December 19, 2000Date of Patent: February 21, 2006Assignee: Intel CorporationInventor: Venkatesan Murali
-
Patent number: 6963684Abstract: A planar lightwave circuit generalized for handling any given band of multiple bands of a wavelength range, including a first grating element handling a first group of bands; and a second grating element handling a second group of bands. The first and second groups of bands overlap in the wavelength range, and may be spaced apart by a fixed wavelength value. By providing two periodic grating elements handling alternating bands, their free spectral range is allowed to expand, improving their roll-off characteristics. By providing separate inputs for each band, wavelength accuracy can be improved. Device flexibility can be further improved by using switch and interleaver fabrics at the inputs and outputs. The resultant device, generalized to handle any given band within a wavelength range, eliminates the need for separate component design and inventory tracking otherwise necessary.Type: GrantFiled: March 15, 2002Date of Patent: November 8, 2005Assignee: JDS Uniphase CorporationInventors: Jyoti Bhardwaj, David Dougherty, Venkatesan Murali, Hiroaki Yamada
-
Patent number: 6928216Abstract: A lithographic process is used to place a marking on a waveguide to indicate optical channels within the waveguide. A photonic component is positioned against the waveguide based on the markings and adjusted until aligned.Type: GrantFiled: September 26, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Venkatesan Murali, Rama K. Shukla
-
Publication number: 20050117853Abstract: An apparatus including a base having a first opening of a dimension suitable to pass a light emission therethrough, a first side wall coupled to the base and having a second opening of a dimension suitable to pass a light emission therethrough, a second side wall coupled to the base and having a reflective component thereon, and the base, the first side wall, and the second side wall define an interior chamber with the reflective component disposed in the interior chamber; and a fiber connector extending from an exterior of the first side wall adjacent the second opening. A method including powering a laser disposed in a substrate coupling a fiber optic cable to an optical subassembly; and aligning the optical assembly over the transceiver board to capture the emitted light from the laser in the fiber optic cable.Type: ApplicationFiled: December 28, 2000Publication date: June 2, 2005Inventors: Venkatesan Murali, Douglas Crafts, Suresh Ramalingam, Brett Zaborsky, Siegfried Fleischer