Abstract: A device has both electronic and photonic components on a shared substrate. The electronic components may include a light source for providing a photonic signal around the substrate to the photonic components.

Abstract: An apparatus comprising a body having dimensions suitable for light transmission therethrough, the body comprising a core extending therethrough, a first portion of the core comprising an index of refraction different than a second portion of the core and a cladding disposed about the core. An optical electronic integrated circuit (OEIC) substrate comprising a plurality of waveguides and a light source emitter coupled to at least one of the plurality of waveguides. A method comprising providing optical signals to an optical electronic integrated circuit (OEIC) through a plurality of waveguides are arranged in a circuit of different paths; and selecting an optical path by the index of refraction of a portion of the core.

Abstract: A device has both electronic and photonic components on a shared substrate. The electronic components may include a light source for providing a photonic signal through the substrate to the photonic components.

Abstract: A lithographic process is used to place a marking on a waveguide to indicate optical channels within the waveguide. A photonic component is positioned against the waveguide based on the markings and adjusted until aligned.

Abstract: A device has both electronic and photonic components on a shared substrate. The electronic components may include a light source for providing a photonic signal around the substrate to the photonic components.

Abstract: A waveguide having an angled surface is created by depositing an optical core material onto a substrate having two levels. In one embodiment, a high density plasma deposition may be used to deposit the optical core material.

Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.

Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.

Abstract: A partial gel step in the underfilling of an integrated circuit that is mounted to a substrate. The process involves dispensing a first underfill material and then heating the underfill material to a partial gel state. The partial gel step may reduce void formation and improve adhesion performance during moisture loading.

Abstract: A substrate which has a first conductive layer that is attached to a first dielectric layer. A second conductive layer is attached to the first dielectric layer. The second conductive layer may be a plated copper material that extends through a via opening of the dielectric and is attached to the first conductive layer. A third conductive layer is attached to the second conductive layer, including a sidewall of the third layer. A second dielectric can be attached to the third conductive layer. The third conductive layer may be a plated nickel-copper composition which improves the adhesion to subsequent layers in the substrate, particularly between the second dielectric and the sidewall of the second conductive layer.

Abstract: A bonding pad structure for use with compliant dielectric materials and a method for wire bonding is described in which a rigid layer is formed between the bonding pad and the compliant dielectric layer. The rigid layer increases the stiffness of the bonding structure such that an effective bond may be achieved by conventional ultrasonic and thermosonic bonding methods.

Abstract: An integrated circuit package which may include a decal that is attached to a substrate which supports an integrated circuit. The decal may have a coefficient of thermal expansion that is different than a coefficient of thermal expansion of the substrate.

Abstract: A method for cutting an integrated circuit die from a wafer. The method may include the step of forming a solder bump on an integrated circuit wafer. The solder bump is then oxidized. The oxidization process may form an outer oxidized layer on the solder bump. An integrated circuit die is cut from the wafer after the oxidization step. The cutting process may include spraying a fluid onto the wafer. The oxidized solder may form a protective layer which reduces the amount of particles and lead hydroxide formed during the cutting process. The integrated circuit die may be mounted to a package substrate by reflowing the solder bump onto a pad of the substrate. The outer oxidized layer may be removed with a flux that is used to reflow the solder bump onto the substrate.

Abstract: A bonding pad structure for use with compliant dielectric materials and a method for wire bonding is described in which a rigid layer is formed between the bonding pad and the compliant dielectric layer. The rigid layer increases the stiffness of the bonding structure such that an effective bond may be achieved by conventional ultrasonic and thermosonic bonding methods.

Abstract: A method for removing Ball Limiting Metallurgy (BLM) layers from the surface of a wafer in the presence of Pb/Sn solder bumps. In one embodiment, the BLM comprises two layers: titanium and copper. After Pb/Sn solder bumps have been formed over the electrical contact pads of the wafer, the BLM copper layer is etched with a H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O solution. While removing the copper layer, the H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O etchant also reacts with the Pb/Sn solder bumps to form a thin PbO protective layer over the surface of the bumps. When the copper layer has been etched away, the titanium layer is etched with a CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O solution. The PbO layer formed over the surface of the Pb/Sn solder bumps remain insoluble when exposed to the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant, thereby preventing the solder bumps from being etched in the presence of the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant.

Abstract: A process for the formation of a titanium nitride/cobalt silicide bilayer for use in semiconductor processing. Titanium and then cobalt are deposited on a silicon substrate by sputter deposition techniques. The substrate is then annealed. During this process the titanium first cleans the silicon surface of the substrate of any native oxide. During the anneal, the titanium diffuses upward and the cobalt diffuses downward. The cobalt forms a high quality epitaxial cobalt silicide layer on the silicon substrate. The titanium layer diffuses upward to the surface of the bilayer. The anneal is carried out in a nitrogen or ammonia ambient, so that a titaniun nitride layer is formed.

Abstract: A process which provides for self-aligned contact hole filling leading to complete planarization and low contact resistance at the same time, without the use of additional lithographic masking procedures is described. Further, the resultant conductive plug eliminates spiking problems between aluminum and silicon during a subsequent alloying process. In an embodiment, a selective polysilicon layer is deposited and appropriately doped; a second undoped selective silicon layer is then deposited, followed by a refractory metal layer, These layers are heated to produce a self-aligned refractory metal silicide plug.