Patents by Inventor Venkatesh P. Gopinath

Venkatesh P. Gopinath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348112
    Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.
    Type: Application
    Filed: November 12, 2018
    Publication date: November 14, 2019
    Inventors: Venkatesh P. Gopinath, Nathan Gonzales
  • Patent number: 10181496
    Abstract: A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 15, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Ming Sang Kwan, Venkatesh P. Gopinath
  • Publication number: 20180205012
    Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.
    Type: Application
    Filed: July 20, 2016
    Publication date: July 19, 2018
    Inventors: Mark T. Ramsbey, Venkatesh P. Gopinath, Jeffrey Allan Shields, Kuei Chang Tsai, Chakravarthy Gopalan, Michael A. Van Buskirk
  • Patent number: 9818939
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 14, 2017
    Assignee: ADESTO TECHNOLOGIES CORPORATION
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Yi Ma, Venkatesh P. Gopinath, Foroozan Sarah Koushan
  • Patent number: 9530495
    Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: December 27, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: John Dinh, Venkatesh P. Gopinath, Nathan Gonzales, Derric Lewis, Deepak Kamalanathan, Ming Sang Kwan
  • Patent number: 9472272
    Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.
    Type: Grant
    Filed: February 22, 2015
    Date of Patent: October 18, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Venkatesh P. Gopinath, Deepak Kamalanathan, Daniel Wang
  • Publication number: 20160247564
    Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.
    Type: Application
    Filed: February 22, 2015
    Publication date: August 25, 2016
    Inventors: Venkatesh P. Gopinath, Deepak Kamalanathan, Daniel Wang
  • Patent number: 9391270
    Abstract: A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 12, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Venkatesh P. Gopinath, Jeffrey Allan Shields, Yi Ma, Chakravarthy Gopalan, Ming Kwon, John Dinh
  • Patent number: 9368198
    Abstract: A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: June 14, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Deepak Kamalanathan, Juan Pablo Saenz Echeverry, Venkatesh P. Gopinath
  • Patent number: 9368206
    Abstract: In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: John Dinh, Ming Sang Kwan, Venkatesh P. Gopinath, Derric Lewis, Shane Hollmer, John R. Jameson, Michael Van Buskirk
  • Publication number: 20160118585
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Yi Ma, Venkatesh P. Gopinath, Foroozan Sarah Koushan
  • Patent number: 9305643
    Abstract: A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: April 5, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Venkatesh P. Gopinath, Foroozan Sarah Koushan, Derric Jawaher Herman Lewis
  • Patent number: 9025396
    Abstract: A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 5, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Foroozan Sarah Koushan, Deepak Kamalanathan, Juan Pablo Saenz Echeverry, Venkatesh P. Gopinath, Janet Wang
  • Patent number: 9007808
    Abstract: Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell; (ii) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state; (iii) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and (iv) performing a recovery of the first data state by reducing the resistance of the first memory cell.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 14, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: John Dinh, Derric Lewis, Venkatesh P. Gopinath, Deepak Kamalanathan, Shane C. Hollmer, Juan Pablo Saenz Echeverry
  • Publication number: 20140293676
    Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.
    Type: Application
    Filed: March 3, 2014
    Publication date: October 2, 2014
    Inventors: Wei Ti Lee, Janet Wang, Chakravarthy Gopalan, Jeffrey Allan Shields, Yi Ma, Kuei Chang Tsai, John Sanchez, John Ross Jameson, Michael Van Buskirk, Venkatesh P. Gopinath
  • Patent number: 8730752
    Abstract: A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Deepak Kamalanathan, Juan Pablo Saenz Echeverry, Venkatesh P. Gopinath
  • Publication number: 20130258753
    Abstract: A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 3, 2013
    Applicant: Adesto Technologies Corporation
    Inventors: Venkatesh P. Gopinath, Foroozan Sarah Koushan, Derric Jawaher Herman Lewis
  • Patent number: 8099705
    Abstract: Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: January 17, 2012
    Assignee: Oracle America, Inc.
    Inventors: Paul J. Dickinson, Venkatesh P. Gopinath, Karl P. Dahlgren, Liang-Chi Chen
  • Patent number: 8021955
    Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: September 20, 2011
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
  • Publication number: 20100281442
    Abstract: Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Paul J. Dickinson, Venkatesh P. Gopinath, Karl P. Dahlgren, Liang-Chi Chen