Patents by Inventor Venkatesh P. Gopinath

Venkatesh P. Gopinath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7001823
    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: February 21, 2006
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
  • Patent number: 6864152
    Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: March 8, 2005
    Assignee: LSI Logic Corporation
    Inventors: Mohammad R. Mirbedini, Venkatesh P. Gopinath, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le
  • Patent number: 6734081
    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. A trench is etched in the integrated circuit substrate. A light barrier layer is then formed in the trench such that the light barrier layer at least partially fills the trench to create an isolation structure, the light barrier layer being adapted for absorbing laser light applied during laser thermal processing, thereby preventing damage to the integrated circuit substrate. For instance, the light barrier layer may be a conductive layer such as polysilicon. A dielectric layer is then formed over the isolation structure. The dielectric layer may be adapted for transferring heat generated by the laser thermal processing to the light barrier layer. For instance, the dielectric layer may be formed through oxidation of a top surface of the light barrier layer.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 11, 2004
    Assignee: LSI Logic Corporation
    Inventors: Helmut Puchner, Venkatesh P. Gopinath
  • Patent number: 6614283
    Abstract: In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: September 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Peter Joseph Wright, Venkatesh P. Gopinath, Todd A. Randazzo
  • Patent number: 6586814
    Abstract: A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Rajiv Patel, David Chan, Arvind Kamath, Ken Rafftesaeth, Venkatesh P. Gopinath
  • Patent number: 6569739
    Abstract: Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: May 27, 2003
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Venkatesh P. Gopinath
  • Patent number: 6566244
    Abstract: A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: May 20, 2003
    Assignee: LSI Logic Corporation
    Inventors: Charles E. May, Venkatesh P. Gopinath, Peter J. Wright