Patents by Inventor Venkatesh Srinivasan

Venkatesh Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240175977
    Abstract: A device, e.g., a radar transceiver, includes a receiver and a transmitter. One such device includes a phase shifter having a first input to receive an oscillating signal and a second input to receive a control signal. The device also includes a signal generator having a quadrature (Q) channel output to output a quadrature phase version of the oscillating signal; and a Q channel mixer having an input coupled to the Q channel output. A feedback path of the device includes a filter having an output and an input coupled to an output of the Q channel mixer, and an integrator having an input coupled to the output of the filter. The integrator has an output coupled to the second input of the phase shifter, in which the integrator outputs the control signal to the phase shifter.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Sreekiran SAMALA, Venkatesh SRINIVASAN, Vijaya B. RENTALA
  • Patent number: 11947031
    Abstract: A radar transceiver includes a receiver. The receiver includes a low noise amplifier a mixer, a baseband filter, an integrator, and a phase shifter. The mixer includes an input coupled to an output of the low noise amplifier. The baseband filter includes an input coupled to an output of the mixer. The integrator includes an input coupled to an output of the baseband filter. The phase shifter includes a control input and an output. The control input is coupled to an output of the integrator.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sreekiran Samala, Venkatesh Srinivasan, Vijaya B. Rentala
  • Publication number: 20240038691
    Abstract: In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Vijaylaxmi Gumaste Khanolkar, Anindya Poddar, Hassan Omar Ali, Dibyajat Mishra, Venkatesh Srinivasan, Swaminathan Sankaran
  • Publication number: 20240020969
    Abstract: An aerial and/or satellite imagery-based, optical system and corresponding method for measuring physical impacts to land-based objects by impact measurands in case of an occurrence of a natural catastrophe event, the natural catastrophe event impacting the objects causing a physical damage. The method and system comprise the steps of capturing by remote airborne and/or spaceborne sensors digital aerial and/or satellite imagery and/or photography of an area affected by the natural catastrophe event and generating a digital natural catastrophe event footprint with a topographical map of the natural catastrophe event based on the captured digital satellite imagery. Finally, parametrizing, by an adaptive vulnerability curve structure, impact measurands for selected objects based on the measured topographical map and generating an impact measurand value for each of the land-based objects based on an event intensity measured by the natural catastrophe event footprint using the vulnerability curve structure.
    Type: Application
    Filed: June 23, 2023
    Publication date: January 18, 2024
    Applicant: Swiss Reinsurance Company Ltd.
    Inventors: David SCHENKEL, Venkatesh SRINIVASAN, Samyadeep SAHA, Abhishek MISHRA
  • Patent number: 11374844
    Abstract: A network appliance having a control plane and a data plane can process substantially every input packet at wire speed in a programmable packet processing pipeline of the data plane. Sensors, which can be processes implemented within the pipeline, can measure parameters of the network traffic flows and of the network appliance in accordance with monitoring policies. Reporting policies can be triggered when any one of many criteria are met by the parameters. The reporting policy can result in a report being sent to an outside recipient. Alternatively, the reporting policy can result in the network appliance implementing additional monitoring or reporting policies.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 28, 2022
    Assignee: Pensando Systems, Inc.
    Inventors: Varagur Chandrasekaran, Vipin Jain, Swaminathan Narayanan, Raghava Kodigenahalli Sivaramu, Venkatesh Srinivasan
  • Publication number: 20220052936
    Abstract: A network appliance having a control plane and a data plane can process substantially every input packet at wire speed in a programmable packet processing pipeline of the data plane. Sensors, which can be processes implemented within the pipeline, can measure parameters of the network traffic flows and of the network appliance in accordance with monitoring policies. Reporting policies can be triggered when any one of many criteria are met by the parameters. The reporting policy can result in a report being sent to an outside recipient. Alternatively, the reporting policy can result in the network appliance implementing additional monitoring or reporting policies.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 17, 2022
    Inventors: Varagur CHANDRASEKARAN, Vipin JAIN, Swaminathan NARAYANAN, Raghava Kodigenahalli SIVARAMU, Venkatesh SRINIVASAN
  • Patent number: 11218336
    Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 4, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Swami Narayanan, Ambrish Mehta, Venkatesh Srinivasan, Raghava Sivaramu, Ayan Banerjee
  • Publication number: 20210356557
    Abstract: A radar transceiver includes a receiver. The receiver includes a low noise amplifier a mixer, a baseband filter, an integrator, and a phase shifter. The mixer includes an input coupled to an output of the low noise amplifier. The baseband filter includes an input coupled to an output of the mixer. The integrator includes an input coupled to an output of the baseband filter. The phase shifter includes a control input and an output. The control input is coupled to an output of the integrator.
    Type: Application
    Filed: November 12, 2019
    Publication date: November 18, 2021
    Inventors: Sreekiran SAMALA, Venkatesh SRINIVASAN, Vijaya B. RENTALA
  • Patent number: 10951531
    Abstract: Aspects of the present disclosure are directed to dynamically adjusting control plane policing throughput of low (or lower) priority control plane traffic to permit higher throughput. The drop rate for low or lower priority control plane traffic can be determined to be above a threshold value. The processor utilization can be determined to be operating under normal utilization (or at a utilization within a threshold utilization value). The control plane policing for control plane traffic for the low or lower class of service can be increased (or decreased) to permit lower class of service control traffic to be transmitted using higher class of service resources without adjusting the priority levels for the lower class of service control traffic.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 16, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Anand Kumar Singh, Venkatesh Srinivasan, Swaminathan Narayanan, Anulekha Chodey, Ambrish Niranjan Mehta, Natarajan Manthiramoorthy
  • Publication number: 20200235959
    Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Swami Narayanan, Ambrish Mehta, Venkatesh Srinivasan, Raghava Sivaramu, Ayan Banerjee
  • Patent number: 10651870
    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkatesh Srinivasan, Kun Shi, Victoria Wang, Nikolaus Klemmer
  • Patent number: 10623207
    Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 14, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Swami Narayanan, Ambrish Mehta, Venkatesh Srinivasan, Raghava Sivaramu, Ayan Banerjee
  • Publication number: 20200074559
    Abstract: A system and a method for computing infrastructural damages is disclosed. In particular, the present invention provides for identifying one or more potential areas to be impacted during a predicted calamity and classifying the one or more potential areas based on severity of impact in said areas. Further, a first group of datasets associated with one or more potential areas are generated. A pre-calamity data is generated based on the first group of datasets using one or more processing techniques. Further, the present invention provides for generating a post-calamity data based on a second group of datasets associated with respective one or more geographical areas actually affected by the predicted calamity. The damage associated with each of the said properties is computed based on at least one of a comparison between the pre-calamity and the post-calamity data, or based on the post-calamity data.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 5, 2020
    Inventors: Venkatesh Srinivasan, Abhishek Mishra, Madhusudhanan Krishnamoorthy, Kumar Ganapathy
  • Patent number: 10516598
    Abstract: Systems, methods, and non-transitory computer-readable storage media for detecting network loops. In some embodiments, a system can identify a network path having multiple hops associated with respective nodes which are configured in a forwarding mode. The system can traverse the network path to identify, for each node from the respective nodes, a respective next hop. Based on the respective next hop for each node, the system can determine whether two or more nodes from the respective nodes have a same respective next hop. When the two or more nodes have the same respective next hop, the system can determine that the network path has a network loop.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: December 24, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Natarajan Manthiramoorthy, Venkatesh Srinivasan, Swaminathan Narayanan, Ambrish Niranjan Mehta, Anand Kumar Singh, Anulekha Chodey
  • Patent number: 10516600
    Abstract: Systems, methods, and non-transitory computer-readable storage media for detecting network loops. In some embodiments, a system can identify a port that is in a blocking state. The blocking state can be for dropping one or more types of packets and preventing the port from forwarding the one or more types of packets. The system can determine a number of packets transmitted through the port by a hardware layer on the system and a number of control packets transmitted through the port by a software layer on the system. The system can determine whether the number of packets is greater than the number of control packets. When the number of packets is greater than the number of control packets, the system can determine that the blocking state has failed to prevent the port from forwarding the one or more types of packets.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 24, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Natarajan Manthiramoorthy, Venkatesh Srinivasan, Swaminathan Narayanan, Ambrish Niranjan Mehta, Anand Kumar Singh, Anulekha Chodey
  • Patent number: 10491508
    Abstract: Systems, methods, and computer-readable storage media for detecting network loops. A system can identify, for each virtual tunnel endpoint (VTEP) from multiple VTEPs in a network, respective media access control address data including the respective local interface media access control addresses of the respective VTEP and respective media access control addresses learned by the respective VTEP. The system can determine whether the VTEPs are running spanning tree protocol (STP), and whether a media access control address learned by a first VTEP matches a respective local interface media access control address of a second VTEP. The system can detect a loop when the media access control address learned by the first VTEP matches the respective local interface media access control address of the second VTEP. The system can also detect a loop when the VTEPs are running STP and the first and second VTEPs see the same STP root bridge.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 26, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Natarajan Manthiramoorthy, Venkatesh Srinivasan, Swaminathan Narayanan, Ambrish Niranjan Mehta, Anand Kumar Singh, Anulekha Chodey
  • Publication number: 20190222223
    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
    Type: Application
    Filed: September 25, 2018
    Publication date: July 18, 2019
    Inventors: Venkatesh Srinivasan, Kun Shi, Victoria Wang, Nikolaus Klemmer
  • Patent number: 10333836
    Abstract: Methods for assisting data forwarding during convergence in a multi-homed network are disclosed. In one aspect, a first leaf node is configured to detect when a second leaf node advertises a set of Ethernet segments which are local to the first leaf and advertise reachability information for the second leaf, indicating itself as a backup for the second leaf during convergence. A spine node that receives advertisement messages from such first and second leaf nodes programs its routing table to indicate the direct route to the second leaf as the primary path and the route to the second leaf via the first leaf as a backup path to forward encapsulated packets destined to the second leaf. Upon failure of the second leaf, when the spine node receives data packets destined to the second leaf, the spine node sends the packets to the first leaf instead of the second leaf.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 25, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Natarajan Manthiramoorthy, Venkatesh Srinivasan, Rajesh Sharma
  • Patent number: 10320838
    Abstract: Systems, methods, and computer-readable media for preventing man-in-the-middle attacks within network, without the need to maintain trusted/un-trusted port listings on each network device. The solutions disclosed herein leverage a host database which can be present on controllers, thereby providing a centralized database instead of a per-node DHCP binding database. Systems configured according to this disclosure (1) use a flood list only for ARP packets received from the controller 116; and (2) unicast ARP packets to the controller before communicating the packets to other VTEPs.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: June 11, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Venkatesh Srinivasan, Ambrish Niranjan Mehta, Anand Kumar Singh, Anulekha Chodey, Natarajan Manthiramoorthy, Swaminathan Narayanan
  • Publication number: 20190116125
    Abstract: Aspects of the present disclosure are directed to dynamically adjusting control plane policing throughput of low (or lower) priority control plane traffic to permit higher throughput. The drop rate for low or lower priority control plane traffic can be determined to be above a threshold value. The processor utilization can be determined to be operating under normal utilization (or at a utilization within a threshold utilization value). The control plane policing for control plane traffic for the low or lower class of service can be increased (or decreased) to permit lower class of service control traffic to be transmitted using higher class of service resources without adjusting the priority levels for the lower class of service control traffic.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Inventors: Anand Kumar Singh, Venkatesh Srinivasan, Swaminathan Narayanan, Anulekha Chodey, Ambrish Niranjan Mehta, Natarajan Manthiramoorthy