Patents by Inventor Venkatesh Srinivasan

Venkatesh Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120098572
    Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).
    Type: Application
    Filed: October 25, 2010
    Publication date: April 26, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Vaibhav Tripathi, Marco Corsi, Venkatesh Srinivasan
  • Publication number: 20120086590
    Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 12, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Patrick Satarzadeh, Venkatesh Srinivasan, Charles Sestok
  • Publication number: 20120086589
    Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 12, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Venkatesh Srinivasan, Patrick Satarzadeh, Marco Corsi
  • Patent number: 8054687
    Abstract: The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a first source, a first drain, and a first gate. The first gate is provided coupled to a first programming capacitor and a first input capacitor. Furthermore, the voltage reference device includes a second floating-gate transistor having a second source, a second drain, and a second gate. The second gate is provided coupled to a second programming capacitor and a second input capacitor. Additionally, the charge difference between the first floating-gate transistor and the second floating-gate transistor is a reference voltage.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 8, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul E. Hasler, Venkatesh Srinivasan, Guillermo J. Serrano, Christopher M. Twigg
  • Patent number: 8018281
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 13, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Patent number: 7915905
    Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: March 29, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
  • Publication number: 20100246267
    Abstract: The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a first source, a first drain, and a first gate. The first gate is provided coupled to a first programming capacitor and a first input capacitor. Furthermore, the voltage reference device includes a second floating-gate transistor having a second source, a second drain, and a second gate. The second gate is provided coupled to a second programming capacitor and a second input capacitor. Additionally, the charge difference between the first floating-gate transistor and the second floating-gate transistor is a reference voltage.
    Type: Application
    Filed: January 21, 2010
    Publication date: September 30, 2010
    Applicant: Georgia Tech Research Corporation
    Inventors: Paul E. Hasler, Venkatesh Srinivasan, Guillermo J. Serrano, Christopher M. Twigg
  • Publication number: 20100197053
    Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 5, 2010
    Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
  • Publication number: 20100176879
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 15, 2010
    Applicant: Georgia Tech Research Center Corp.
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Publication number: 20100125529
    Abstract: Systems and methods are provided for renting a peripheral storage entity to a remote client. From the service provider's vantage, one method transceives negotiation signals between a remote first client (the user) and a service provider, via a network link. Using the negotiation signals, the service provider agrees to rent a peripheral storage entity to the first client, and sends digital content from the peripheral storage entity via the network link to the remote first client. The peripheral storage entity may be located with the service provider or with a remote second client. System and methods are also provided from the perspective of remote clients that are either receiving or supplying peripheral storage entity content.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 20, 2010
    Inventors: Venkatesh Srinivasan, Ravi Subrahmanyan, Michel Billard, Murali Narayanaswamy
  • Patent number: 7719299
    Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: May 18, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
  • Patent number: 7714650
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 11, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Publication number: 20090251164
    Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
  • Publication number: 20070210860
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Application
    Filed: August 30, 2006
    Publication date: September 13, 2007
    Applicant: Georgia Tech Research Corp.
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Publication number: 20050221456
    Abstract: The invention is directed to a method for the production of taxanes by culturing suspension cells of Taxus sp. in a nutrient medium that comprises an indanoyl amino acid. The indanoyl amino acid may be added in batch mode or in a feed stream at any time of the culturing. In particular, synthetic compounds 6-Ethyl-indanoyl-isoleucine, 6-Bromoindanoyl isoleucine and 1-oxo-indane-carboxy-(L)-Isoleucine-methyl ester amide (1-OII) have been found to increase taxane production from Taxus cell cultures.
    Type: Application
    Filed: February 14, 2005
    Publication date: October 6, 2005
    Applicant: Phyton Biotech, Inc.
    Inventors: Venkatesh Srinivasan, Jennifer Alford, Harald Heckenmuller, Braden Roach