Abstract: For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier.

Abstract: Systems and methods are provided for renting a peripheral storage entity to a remote client. From the service provider's vantage, one method transceives negotiation signals between a remote first client (the user) and a service provider, via a network link. Using the negotiation signals, the service provider agrees to rent a peripheral storage entity to the first client, and sends digital content from the peripheral storage entity via the network link to the remote first client. The peripheral storage entity may be located with the service provider or with a remote second client. System and methods are also provided from the perspective of remote clients that are either receiving or supplying peripheral storage entity content.

Abstract: In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR).

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: Blixers, which are a relatively recent development, have not be studied as extensively as many older circuit designs. Here, a blixer is provided that improves linearity and reduces noise over other conventional blixer designs. To accomplish this, the blixer provided here uses a differential amplifier and/or a dummy path within its mixing circuit to perform noise reduction (and improve linearity).

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier.

Abstract: In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR).

Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Abstract: For high speed amplifiers, the parasitic capacitances between a differential input pairs and a cascoded bias network can introduce a pole that can affect performance. Here, a feedforward network has been provided that compensates for this pole by introducing a zero that effectively cancels the pole, moving the next parasitic without any additional power. This is generally accomplished by using a pair of feedforward capacitors coupled across the transistors of the cascoded bias network, which reduced power consumption.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Blixers, which are a relatively recent development, have not be studied as extensively as many older circuit designs. Here, a blixer is provided that improves linearity and reduces noise over other conventional blixer designs. To accomplish this, the blixer provided here uses a differential amplifier and/or a dummy path within its mixing circuit to perform noise reduction (and improve linearity).

Abstract: The present invention relates to the production of alkaloids from Liliaceae cell culture.

Abstract: The present invention provides a method and system for generating testing templates suitable for the testing of ERP package based solutions. Functional test cases are prepared from real-life business processes as defined by industry standard and best practices. The test cases are reusable and can be used for any future ERP package-related projects, thereby reducing test planning effort and duration.

Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: A load current compensating output buffer circuit and method are disclosed. The circuit includes a buffer amplifier coupled to a supply voltage and the inverting input receives an input voltage and the non-inverting input couples to an output capacitive load. A feedback impedance with a variable resistance circuit and a Miller capacitance in series is coupled to an output of the buffer amplifier and the capacitive load. A pass transistor couples to the supply voltage and the output capacitive load, the pass transistor having a gate terminal coupled to the output of the output buffer amplifier and the feedback impedance, a load current passing through the pass transistor. A sense circuit is configured to sense the load current and apply a control voltage to the variable resistance circuit to vary the resistance of the variable resistance circuit based on the load current.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.