Abstract: Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a magnetic ring is embedded in the substrate. In an embodiment, a loop is around the magnetic ring. In an embodiment, the loop is conductive and comprises a first via through the substrate, a second via through the substrate, and a trace over a surface of the substrate, where the trace electrically couples the first via to the second via.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate with a first optical waveguide within the substrate, an optical ring resonator within the substrate, and a second optical waveguide within the substrate. In an embodiment, the first optical waveguide and the second optical waveguide are offset from each other in a vertical direction and a horizontal direction. In an embodiment, the optical ring resonator is between the first optical waveguide and the second optical waveguide in the horizontal direction.

Abstract: Embodiments disclosed herein include an apparatus that comprises a first layer with a first dielectric material, a second layer with a second dielectric material embedded within the first layer, where the second dielectric material has a higher index of refraction than the first dielectric material, and a first contact that is electrically conductive embedded in the first layer. In an embodiment, a third layer comprises a third dielectric material, a fourth layer comprising a fourth dielectric material and is embedded within the third layer, where the fourth dielectric material has a higher index of refraction than the third dielectric material, and a second contact that is electrically conductive embedded in the third layer. In an embodiment, the first layer directly contacts the third layer, the second layer directly contacts the fourth layer, and the first contact directly contacts the second contact.

Abstract: Devices and systems with shifted out-of-plane light propagation, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a first optical waveguide, a second optical waveguide, and one or more passive optical components. The first and second optical waveguides are optically coupled via the passive optical components. Moreover, the passive optical components are to shift light propagation out of plane between the first and second optical waveguides.

Abstract: Technologies for a compact and low-crosstalk multilayer waveguide stack are disclosed. In an illustrative embodiment, a photonic integrated circuit (PIC) die includes a 3D array of waveguides arranged in a multilayer stack. Individual waveguides have a propagation constant different from the propagation constant of neighboring waveguides, which can reduce crosstalk between neighboring waveguides. In an illustrative embodiment, the propagation constant can be controlled by changing the width of individual waveguides. In other embodiments, the propagation constant can be controlled by changing any suitable parameter, such as the height of the waveguides, the core of the waveguides, the cladding of the waveguides, etc.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a buildup layer is over the core. In an embodiment, a patch antenna with a first patch is under the core, and a second patch is over a surface of the core opposite from the first patch. In an embodiment, the electronic package further comprises a via through the core and coupled to the patch antenna.

Abstract: Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate with a first surface and a second surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a via opening through the substrate, where sidewalls of the via opening have a root mean squared (RMS) surface roughness that is approximately 100 nm or greater. In an embodiment, the electronic package further comprises a liner over the sidewalls of the via opening, where an RMS surface roughness of the liner is approximately 50 nm or smaller. An electronic package may further comprise a via through the via opening.

Abstract: Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

Abstract: Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Abstract: Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

Abstract: Embodiments disclosed herein comprise a method for assembling an interposer. In an embodiment, the method comprises assembling a structure over a carrier substrate, where the structure is mechanically coupled to the carrier substrate by a debond film. In an embodiment, the structure comprises an organic dielectric layer, and the debond film comprises an inorganic layer. The method may further comprise ablating at least a portion of the debond film with a laser. In an embodiment, a wavelength of the laser is within an infrared range. The method may further comprise separating the carrier substrate from the structure.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate with a first surface and a second surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a via opening through the substrate, where sidewalls of the via opening have a root mean squared (RMS) surface roughness that is approximately 100 nm or greater. In an embodiment, the electronic package further comprises a liner over the sidewalls of the via opening, where an RMS surface roughness of the liner is approximately 50 nm or smaller. An electronic package may further comprise a via through the via opening.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Abstract: Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Abstract: Various aspects may provide a handling assembly. The handling assembly may include a body with a component-handling surface. The component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. The handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. In the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.

Abstract: A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding process a biphilic surface on the IC die structure or substrate structure may facilitate liquid droplet-based fine alignment of the IC die structure to a host structure. Prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.